• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.195-203
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• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.118-118
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• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.904-906
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• 2009

Organic field-effect transistor (OFET) memory is an emerging device for its potential to realize light-weight, low cost flexible charge storage media. Here we report on a solution-processed poly[9,9-dioctylfluorenyl-2,7-diyl]-co-(bithiophene)] (F8T2) nano floating-gate memory (NFGM) with top-gate/bottom-contact device configuration. A reversible shift in the threshold voltage ($V_{Th}$) and the reliable memory characteristics were achieved by incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative electrons at the interface between polystyrene and cross-linked poly(4-vinylphenol).

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.18-26
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• 2004

Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.20.1-20.1
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• 2011

The nano-sized quantum structure has been an attractive candidate for investigations of the fundamental physical properties and potential applications of next-generation electronic devices. Metal nano-particles form deep quantum wells between control and tunnel oxides due to a difference in work functions. The charge storage capacity of nanoparticles has led to their use in the development of nano-floating gate memory (NFGM) devices. When compared with conventional floating gate memory devices, NFGM devices offer a number of advantages that have attracted a great deal of attention: a greater inherent scalability, better endurance, a faster write/erase speed, and more processes that are compatible with conventional silicon processes. To improve the performance of NFGM, metal nanocrystals such as Au, Ag, Ni Pt, and W have been proposed due to superior density, a strong coupling with the conduction channel, a wide range of work function selectivity, and a small energy perturbation. In the present study, bismuth metal nanocrystals were self-assembled within high-k $Bi_2Mg_{2/3}Nb_{4/3}O_7$ (BMN) films grown at room temperature in Ar ambient via radio-frequency magnetron sputtering. The work function of the bismuth metal nanocrystals (4.34 eV) was important for nanocrystal-based nonvolatile memory (NVM) applications. If transparent NFGM devices can be integrated with transparent solar cells, non-volatile memory fields will open a new platform for flexible electron devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.325-327
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• 2011

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a $SiO_2/Si$ substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.255-255
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• 2009

In this work, nonvolatile nano-floating gate memory devices were fabricated with ZnO films and Al nanoparticles using the sputtering method on a glass substrate. Al nanoparticles acted as floating gate nodes in the devices. The fabricated device exhibits a threshold voltage shift of 1.7 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.79-79
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• 2013

Quantum-structures with nanoparticles have been attractive for various electronic and photonic devices [1,2]. In recent, nonvolatile memories such as nano-floating gate memory (NFGM) and resistance random access memory (ReRAM) have been studied using silicides, metals, and metal oxides nanoparticles [3,4]. In this study, we fabricated nonvolatile memories with silicides (WSi2, Ti2Si, V2Si) and metal-oxide (Cu2O, Fe2O3, ZnO, SnO2, In2O3 and etc.) nanoparticles embedded in polyimide matrix, and photovoltaic device also with SiC nanoparticles. The capacitance-voltageand current-voltage data showed a threshold voltage shift as a function of write/erase voltage, which implies the carrier charging and discharging into the metal-oxide nanoparticles. We have investigated also the electrical properties of ReRAM consisted with the nanoparticles embedded in ZnO, SiO2, polyimide layer on the monolayered graphene. We will discuss what the current bistability of the nanoparticle ReRAM with monolayered graphene, which occurred as a result of fully functional operation of the nonvolatile memory device. A photovoltaic device structure with nanoparticles was fabricated and its optical properties were also studied by photoluminescence and UV-Vis absorption measurements. We will discuss a feasibility of nanoparticles to application of nonvolatile memories and photovoltaic devices.

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.155-165
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• 2010

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.