• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.71-76
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• 2012

A chip interconnection technology for smart fabrics was investigated by using flip-chip bonding of SnBi low-temperature solder. A fabric substrate with a Cu leadframe could be successfully fabricated with transferring a Cu leadframe from a carrier film to a fabric by hot-pressing at $130^{\circ}C$. A chip specimen with SnBi solder bumps was formed by screen printing of SnBi solder paste and was connected to the Cu leadframe of the fabric substrate by flip-chip bonding at $180^{\circ}C$ for 60 sec. The average contact resistance of the SnBi flip-chip joint of the smart fabric was measured as $9m{\Omega}$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.193-215
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• 2003

Fracture Mechanism of Flip Chip Electromigration Failure - Mostly caused by Cathode Depletion at the UBM/Solder Interface Guideline to Increase Electromigration Resistance Material Selection: Sn/Ag(/Cu) > Pb/63Sn Cu UBM > Ni UBM (but, Solder Material combination) UBM Design: thick UBM is preferable (but, Stress Issue) Pad open/UBM size: as large as possible (but, pad size & pitch limit)

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.545-546
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• 2010

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.749-750
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• 2011

• Journal of Welding and Joining
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• v.30 no.6
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• pp.113-119
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• 2012

Ultrasonic bonding is the novel packaging method for flip-chip with high yield and low-temperature bonding. The bonding module is a core part of the bonding machine, which can transfer the ultrasonic energy into the bonding spot. In this paper, we propose topology optimization technique which can make new design of boding modules due to the constraints on resonance frequency and mode shapes. The designed bonding module using topology optimization was fabricated in order to evaluate the bonding performance and reliable operation during the continuous bonding process. The actual production models based on the proposed design satisfied the target frequency range and ultrasonic power. The bonding test was performed using flip-chip with lead-free Sn-based bumps, the results confirmed that the bonding strength was sufficient with the designed bonding modules. Also the performance degradation of the bonding module was not observed after the 300-hour continuous process with bonding conditions.

• Journal of the Korean institute of surface engineering
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• v.36 no.2
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• pp.214-225
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• 2003

Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.5
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• pp.559-563
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• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.145-164
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• 2004

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.47-66
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• 2006

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.21-35
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• 2006