• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 The IMAPS-Korea Workshop 2001 Emerging Technology on packaging
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• pp.95-99
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• 2001

Cu is considered as a promising alternative interconnection material to Al-based interconnection materials in Si-based integrated circuits due to its low resistivity and superior resistance to the electromigration. New humping and UBM material systems for solder flip chip interconnection of Cu pads were investigated using electroless-plated copper (E-Cu) and electroless-plated nickel (E-Ni) plating methods as low cost alternatives. Optimally designed E-Ni/E-Cu UBM bilayer material system can be used not only as UBMs for solder bumps but also as bump itself. Electroless-plated E-Ni/E-Cu bumps assembled using anisotropic conductive adhesives on an organic substrate is successfully demonstrated and characterized in this study

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• Journal of Advanced Marine Engineering and Technology
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• 제37권4호
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• pp.351-357
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• 2013

플립칩 패키징에서 언더필 공정은 칩과 기판 사이를 에폭시로 채워서 본딩하는 공정으로 제품의 신뢰성 향상을 위해 수행되어 진다. 이 언더필 공정은 모세관 현상에 의해서 이루어지는데 유체의 계면과 범프의 배열이 계면 운동에 미치는 영향으로 인하여 공정 중 예기치 않은 공기층을 형성하게 된다. 본 연구에서는 모세관 언더필 유동에서 나타나는 비정상 계면 유동을 가시화하여 범프 배열에 따른 레이싱 효과와 계면의 병합 현상에 대하여 고찰하였다. 그 결과, 플립칩 내부의 범프가 고밀도일수록 유체의 흐름방향과 수직방향의 유동이 더욱 활발하게 진행되어 더 많은 공기층이 형성되었으며, 엇갈린 배열일 경우 직각 배열에 비해 이러한 현상이 더 지배적으로 나타난다.

• 대한금속재료학회지
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• 제49권5호
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• pp.411-418
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• 2011

The current study investigates the electroplating characteristics of Sn-Cu eutectic micro-bumps electroplated on a Si chip for flip chip application. Under bump metallization (UBM) layers consisting of Cr, Cu, Ni and Au sequentially from bottom to top with the aim of achieving Sn-Cu bumps $10\times10\times6$ ${\mu}m$ in size, with 20${\mu}m$ pitch. In order to determine optimal plating parameters, the polarization curve, current density and plating time were analyzed. Experimental results showed the equilibrium potential from the Sn-Cu polarization curve is -0.465 V, which is attained when Sn-Cu electro-deposition occurred. The thickness of the electroplated bumps increased with rising current density and plating time up to 20 mA/$cm^2$ and 30 min respectively. The near eutectic composition of the Sn-0.72wt%Cu bump was obtained by plating at 10 mA/$cm^2$ for 20 min, and the bump size at these conditions was $10\times10\times6$ ${\mu}m$. The shear strength of the eutectic Sn-Cu bump was 9.0 gf when the shearing tip height was 50% of the bump height.

• 마이크로전자및패키징학회지
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• 제15권1호
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• pp.7-18
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• 2008

This paper reviews the current development of an ultra-slim SiP for Radio Frequency (RF) application, in which three flip chips, additional passive components and Surface Acoustic Wave (SAW) filters are integrated side-by-side. A systematic investigation is carried out for the design optimization, process and reliability improvement of the package, which comprises several aspects: a design study based on the 3D thermo-mechanical finite element analysis of the packaging, the determination of stress, warpage distribution, critical failure zones, and the figuration of the effects of material properties, process conditions on the reliability of package. The optimized material sets for manufacturing process were determined which can reduce the number of testing samples from 75 to 2. In addition the molded underfilling (MUF) process is proposed which not only saves one manufacturing process, but also improves the thermo-mechanical performance of the package compared with conventional epoxy underfilling process. In the end, JEDEC's moisture sensitivity test, thermal cycle test and pressure cooker tests have also been carried out for reliability evaluation. The test results show that the optimized ultra-slim SiP has a good reliability performance.

• 마이크로전자및패키징학회지
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• 제12권3호
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• pp.243-251
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• 2005

페리퍼럴 어레이 플립칩의 온도 분포를 실측하여 열원의 기하학적 형상, 소자의 크기, 그리고 보호막 개구 크기 변화에 따른 소자의 열 성능을 측정하였다. 열원의 크기가 작고, 플립칩 솔더 범프에서 먼 중앙 열원의 경우가 전 면적 열원에 비해서 소자의 온도가 매우 높았다. 여기에 더해, 보호막 개구의 모양 변화에 의한 접촉 면적의 증가를 통해 소자의 최대 온도를 낮출 수가 있었다. 중앙 열원을 갖고 원형 개구에 2 (watts)의 전력이 가해지는 경우, $3(mm)\times3(mm)$크기 소자의 최대 온도는 약 $110(^{\circ}C)$이고, 이에 반해 $1.5(mm)\times1.8(mm)$ 크기 소자의 최대 온도는 약 $90(^{\circ}C)$ 이었다. 또한 보호막 개구의 모양을 원형 개구에서 잘린 사각형 개구로 변화시키면서 접촉 면적을 증가시킨 경우, $3(mm)\times3(mm)$ 크기의 소자와 중앙 열원을 갖는 경우에서 약 $10(^{\circ}C)$의 온도 감소를 나타내었다. 따라서 열원 소자의 위치와 크기, 소자의 크기, 그리고 개구 면적에 따른 솔더의 접촉 면적에 따라 플립칩의 열 성능이 현격한 차이를 나타내고 있음을 알 수 있다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.129-133
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• 2001

In this paper, hermetic sealing was studied fur wafer level packaging of the MEMS devices. With the flip-chip bonding method, this B-stage epoxy sealing will be profit to MEMS device sealing and further more RF-MEMS device sealing. B-stage epoxy can be cured 2-step and hermetic sealing can be obtained. After defining $500{\mu}{\textrm}{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was then aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line were maintained during the sealing process. The height of the seal-line was controlled within $\pm0.6${\mu}{\textrm}{m}$ and the strength was measured to about 20MPa by pull test. The leak rate of the epoxy was about $10^7$ cc/sec from the leak test.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기물성,응용부문
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• pp.30-32
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• 2005

This paper reports on an LTCC-based packaging method using Au/Sn eutectic bonding process for RF MEMS applications. The proposed packaging structure was realized by a micromachining technology. An LTCC substrate consists of metal filled vertical via feedthroughs for electrical interconnection and Au/Sn sealing rim for eutectic bonding. The LTCC capping substrate and the glass bottom substrate were aligned and bonded together by a flip-chip bonding technology. From now on, shear strength and He leak rate will be measured then the fabricated package will be compared with the LTCC package using BCB adhesive bonding method which has been researched in our previous work.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.39-47
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• 2002

Heat is always the root of stress acting upon the electronic package, regardless of the heat due to the device itself during operation or working under the adverse environment. Due to the significant mismatch in coefficient of thermal expansion (CTE) and the thermal conductivity (K) of the packaging components, on one hand intensive research has been conducted in order to enhance the device reliability by minimizing the mechanical stressing and deformation within the package. On the other hand the effectiveness of different thermal enhancements are pursued to dissipate the heat to avoid the overheating of the device. However, the interactions between the thermal-mechanical loading has not yet been address fully. in articular when the temperature gradient is considered within the package. To address the interactions between the thermal loading upon the mechanical stressing condition. coupled-field analysis is performed to account the interaction between the thermal and mechanical stress distribution. Furthermore, process induced defects are also incorporated into the analysis to determine the effects on thermal conducting path as well as the mechanical stress distribution. It is concluded that it feasible to consider the thermal gradient within the package accompanied with the mechanical analysis, and the subsequent effects of the inherent defects on the overall structural integrity of the package are discussed.

• 마이크로전자및패키징학회지
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• 제22권2호
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• pp.55-59
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• 2015

Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.