• 한국기계가공학회지
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• 제15권4호
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• pp.16-22
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• 2016

This study is a structural analysis of 3" Cryogenic Safety Breakaway Coupling using a manufactured product from KLAW Company. Breakaway coupling is very important in the pipe system, especially when transporting fuel or gas in the pipeline. For the analysis of the patent infringement target, Dover and KLAW Company's technologies (US 08127785, EP 0764809) were analyzed. Finally, the flip-flap valve overlap was measured after combining the breakaway coupling through 3D modeling, and the valve overlap had a 0.7mm measurement value from the height gauge. The safety breakaway coupling consisted of a total of 62 pieces (body: 42, valve module: 21).

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.254-256
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• 2007

In this paper, the effects of the reflow number in the mechanical reliability of flip chip solder joint was investigated by flip chip shear test and thermal shock test. For evaluation mechanical reliability of flip chip, We experiment that specimens were operated 3-times, 6-times, 9-times, 12-times under reflow Process. After shear test and thermal shock test, We measured max shear strength and coming first crack number of thermal cycle. And We observe fracture surface and cross section by using SEM(Scanning Electron Microscope) and optical scope. In the results, the more specimens were operated reflow process, the more decreased maximum shear strength and number of thermal cycle.

• 대한화학회지
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• 제64권3호
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• pp.145-152
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• 2020

Flip-flop rate constants were measured by dithionite assay of NBD-PE fluorescence in DMPC/POPC vesicles made of various DMPC/POPC ratios. The activation energy, enthalpy, entropy, and free energy were determined based on the transition state theory. We found that the activation energy, enthalpy, and entropy increased as the amount of POPC increased, but the activation free energy was almost constant. These experimental results and other similar studies allow us to propose that the POPC molecules included in DMPC vesicles affect the flip-flop motion of NBD-PE in DMPC/POPC vesicles via increasing the packing order of the ground state of the bilayer of the vesicles. The increase in the packing order in the ground state seems to be a result of the effect of the overall molecular shape of POPC with a monounsaturated tail group, rather than the effect of the longer tail group.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2005년도 춘계학술발표대회 개요집
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• pp.19-21
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• 2005

The ball shea. tests for ball grid array (BGA) and flip chip packages were carried out with different displacement rates to find out the optimum condition of the displacement rate for this test. The BGA packages consisted of two different kinds of solder balls (eutectic Sn-37wt.%Pb and Sn-3.5wt.%Ag) and electroplated Au/Ni/Cu substrate, whereas the flip chip package consisted of electroplated Sn-37Pb solder and Cu UBM. The packages were reflowed up to 10 times, or aged at 443 K up to 21 days. The variation of the displacement rate resulted in the variations of the shear properties such as shear force, displacement rate at break, fracture mode and strain rate sensitivity. The increase in the displacement rate led to the increase of the shear force and brittleness of solder joints.

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.17-24
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• 2012

Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of $150^{\circ}C$ or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

• 대한전자공학회논문지
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• 제16권2호
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• pp.7-14
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• 1979

Integrated Injecton Logic의 설계를 npn transistor 의 상향전류증폭율, βu 을 중심으로 하여 검토하였다. I2L 기본회로의 DC, AC특성과 npn transistor의 베이스 전류성분을 측정하기 위하여 test structure를 제작하였으며 또한 I2L T flip-flop도 설rP, 제작하였다. 제작된 test structure의 특성은 βe가 10, speed-power product가 2.6p.J/gate, 최소 전달지연 시간이 36 nsec 였으며 T flip-flop은 3.5 MHz 까지 동작하였다.

• IEIE Transactions on Smart Processing and Computing
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• 제2권4호
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• pp.208-215
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• 2013

Early iterations of the existing Global Positioning System (GPS)-based or radio lateration technique-based vehicle localization algorithms suffer from flip ambiguities, forged relative location information and location information exchange overhead, which affect the subsequent iterations. This, in turn, results in an erroneous neighbor-vehicle map. This paper proposes an extended information overlap measure (EIOM) algorithm to reduce the flip error rates by exchanging the neighbor-vehicle presence features in binary information. This algorithm shifts and associates three pieces of information in the Moore neighborhood format: 1) feature information of the neighboring vehicles from a vision-based environment sensor system; 2) cardinal locations of the neighboring vehicles in its Moore neighborhood; and 3) identification information (MAC/IP addresses). Simulations were conducted for multi-lane highway scenarios to compare the proposed algorithm with the existing algorithm. The results showed that the flip error rates were reduced by up to 50%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.347-350
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• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.247-251
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• 2002

In this paper the maximum current carrying capability of ACAs flip chip joint is investigated based on two failure mechanisms: (1) degradation of the interface between gold stud bumps and aluminum pads; and (2) ACA swelling between chips and substrates under high current stress. For the determination of the maximum allowable current, bias stressing was applied to ACAs flip chip joint. The current level at which current carrying capability is saturated is defined as the maximum allowable current. The degradation mechanism under high current stress was studied by in-situ monitoring of gold stud bump-aluminum pad ACA contact resistance and also ACA junction temperature at various current level. The cumulative failure distributions were used to predict the lifetime of ACAs flip chip joint under high current stressing. These experimental results can be used to better understand and to improve the current carrying capability of ACA flip chip joint.