• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.337-345
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• 2016

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

• Korean Journal of Metals and Materials
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• v.50 no.10
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• pp.785-792
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• 2012

A new flip chip structure consisting of interlocking joints locally surrounded by non-conductive adhesive was investigated in order to improve the contact resistance characteristics and prevent the parasitic capacitance increase. The average contact resistance of the interlocking joints was substantially reduced from $135m{\Omega}$ to $79m{\Omega}$ by increasing the flip chip bonding pressure from 85 MPa to 185 MPa. Improvement of the contact resistance characteristics at higher bonding pressure was attributed not only to the increased contact area between Cu chip bumps and Sn pads, but also to the severe plastic deformation of Sn pads caused during formation of the interlocking-joint structure. The parasitic capacitance increase due to the non-conductive adhesive locally surrounding the flip chip joints was estimated to be as small as 12.5%.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.189-192
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• 2000

We fabricated rapid single-flux-quantum RS flip-flop circuits with and without Y$_1$Ba$_2$Cu$_3$O$_{7-{\delta}}$(YBCO) ground plane. The circuit consists of SNS-type ramp-edge Josephson junctions that have cobalt-doped YBCO and Sr$_2$AITaO$_6$(SAT) for barrier layer and insulator layer, respectively. The fabricated Josephson junction showed a typical RSJ-like current-voltage(I-V) characteristics above 50K. We sucessfuly demonstrated RS flip-flop at temperatures around 50K. The RS flip-flop fabricated on ground plane showed more definite set and reset state in voltage-flux(V-${\phi}$) modulation curve for read SQUID, which may be attributed to a shielding effect of the YBCO ground plane.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.10
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• pp.676-681
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• 2015

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.49-52
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• 2022

As the difficulty of flip chip products increase, interest in stable PKG material technology from the viewpoint of reliability is increasing. Currently, the representative of poor reliability that are mainly occurring in flip chip PKG are Sn bridge and Cu dendrite. Two type defects are caused by void generated by the flux residue around the bump. In order to essentially minimize the risk of this type of reliability failure, the linkage between the composition of Molded Under-fill (MUF) and flux, which is related material, was reviewed. In this study, the correlation between base resin and filler, which is the main component of MUF, and flux, was defined, and the material composition design was carried out by refer to lesson learn. With the current material composition, it was confirmed that moisture absorption reliability 85%/85%/24hrs pass result and void did not occur during destructive analysis, and developed MUF has shown flux immunity improving result in flip Chip PKG. We think this study can be used in yield enhancement of flip chip process and give insights to study in compatibility between MUF and flux.

• Journal of Welding and Joining
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• v.26 no.3
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• pp.30-36
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• 2008

A flip-chip bonding system using IR laser with a wavelength of 1064 nm was developed and associated process parameters were analyzed using Taguchi methods. An infrared laser beam is designed to transmit through a silicon chip and used for transferring laser energy directly to micro-bumps. This process has several advantages: minimized heat affect zone, fast bonding and good reliability in the microchip bonding interface. Approximately 50 % of the irradiated energy can be directly used for bonding the solder bumps with a few seconds of bonding time. A flip-chip with 120 solder bumps was used for this experiment and the composition of the solder bump was Sn3.0Ag0.5Cu. The main processing parameters for IR laser flip-chip bonding were laser power, scanning speed, a spot size and UBM thickness. Taguchi methods were applied for optimizing these four main processing parameters. The optimized bump shape and its shear force were modeled and the experimental results were compared with them. The analysis results indicate that the bump shape and its shear force are dominantly influenced by laser power and scanning speed over a laser spot size. In addition, various effects of processing parameters for IR laser flip-chip bonding are presented and discussed.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.39-44
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• 2015

We investigated the effect of CNT-Ag composite pad on the contact resistance of flip-chip joints, which were formed by flip-chip bonding of Cu/Au chip bumps to Cu substrate metallization using anisotropic conductive adhesive. Lower contact resistances were obtained for the flip-chip joints which contained the CNT-Ag composite pad than the joints without the CNT-Ag composite pad. While the flip-chip joints with the CNT-Ag composite pad exhibited average contact resistances of $164m{\Omega}$, $141m{\Omega}$, and $132m{\Omega}$ at bonding pressures of 25 MPa, 50 MPa, and 100 MPa, the flip-chip joints without the CNT-Ag composite pad had an average contact resistance of $200m{\Omega}$, $150m{\Omega}$, and $140m{\Omega}$ at each bonding pressure.

• Journal of the Korea Convergence Society
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• v.9 no.6
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• pp.209-215
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• 2018

The college liberal arts mathematics is opened as a required course in science and engineering field, but students with low achievement experience difficulty in learning. Therefore, flip learning, which is well known as an effective teaching method based on self-led and learner, is suggested as an alternative. However, some problems are pointed out in this pedagogy. As an alternative to flip learning, we apply flip PBL classes that apply PBL to flip learning to general math subjects to supplement the problems of existing flip learning classes and increase interest in mathematics I want to know the effectiveness of whether it can be done. In this study, we investigated the educational effectiveness of the comparison study between the experimental group applying flip PBL class and the control group applying the existing flip learning class. First, the experimental group showed higher than the control group by 22 points Second, in the reflection journal analysis, in contrast to the control group, there was a positive effect on the improvement of the interest of the mathematics in the experimental group, It is expected that it will be applied as a teaching method that can complement the learning.