• Title/Summary/Keyword: flip

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Solid Modeling of UBM and IMC Layers in Flip Chip Packages (플립칩 패키지에서 UBM 및 IMC 층의 형상 모델링)

  • Shin, Ki-Hoon;Kim, Joo-Han
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.16 no.6
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    • pp.181-186
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    • 2007
  • UBM (Under Bump Metallurgy) of flip chip assemblies consists of several layers such as the solder wetting, the diffusion barrier, and the adhesion layers. In addition, IMC layers are formed between the solder wetting layers (e.g. Cu, Ni) and the solder. The primary failure mechanism of the solder joints in flip chips is widely known as the fatigue failure caused by thermal fatigues or electromigration damages. Sometimes, the premature brittle failure occurs in the IMC layers. However, these phenomena have thus far been viewed from only experimental investigations. In this sense, this paper presents a method for solid modeling of IMC layers in flip chip assemblies, thus providing a pre-processing tool for finite element analysis to simulate the IMC failure mechanism. The proposed modeling method is CSG-based and can also be applied to the modeling of UBM structure in flip chip assemblies. This is done by performing Boolean operations according to the actual sequences of fabrication processes

Flip Chip Assembly Using Anisotropic Conductive Adhesives with Enhanced Thermal Conductivity

  • Yim, Myung-Jin;Kim, Hyoung-Joon;Paik, Kyung-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.1 s.34
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    • pp.9-16
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    • 2005
  • This paper presents the development of new anisotropic conductive adhesives with enhanced thermal conductivity for the wide use of adhesive flip chip technology with improved reliability under high current density condition. The continuing downscaling of structural profiles and increase in inter-connection density in flip chip packaging using ACAs has given rise to reliability problem under high current density. In detail, as the bump size is reduced, the current density through bump is also increased. This increased current density also causes new failure mechanism such as interface degradation due to inter-metallic compound formation and adhesive swelling due to high current stressing, especially in high current density interconnection, in which high junction temperature enhances such failure mechanism. Therefore, it is necessary for the ACA to become thermal transfer medium to improve the lifetime of ACA flip chip joint under high current stressing condition. We developed thermally conductive ACA of 0.63 W/m$\cdot$K thermal conductivity using the formulation incorporating $5 {\mu}m$ Ni and $0.2{\mu}m$ SiC-filled epoxy-bated binder system to achieve acceptable viscosity, curing property, and other thermo-mechanical properties such as low CTE and high modulus. The current carrying capability of ACA flip chip joints was improved up to 6.7 A by use of thermally conductive ACA compared to conventional ACA. Electrical reliability of thermally conductive ACA flip chip joint under current stressing condition was also improved showing stable electrical conductivity of flip chip joints. The high current carrying capability and improved electrical reliability of thermally conductive ACA flip chip joint under current stressing test is mainly due to the effective heat dissipation by thermally conductive adhesive around Au stud bumps/ACA/PCB pads structure.

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Analysis of tail flip of the target prawn at the time of penetrating mesh in water flow by tank experiments

  • KIM, Yonghae;GORDON, Malcolm S.
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.52 no.4
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    • pp.308-317
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    • 2016
  • The tail flip of the decapod shrimp is a main feature in escaping behavior from the mesh of the codend in the trawl. The characteristics of tail flip in target prawn was observed and analyzed in a water tunnel in respect of flow condition and mesh penetration by a high speed video camera (500 fps). The tail bending angle or bending time in static water was significantly different than in flow water (0.7 m/s) and resultantly the angular velocity in static water was significantly higher than in flow water when carapace was fixed condition. When escaping through vertical traverse net panel in water flow the relative moving angle and relative passing angle to flow direction during tail flip, it significantly decreases the number of shrimps escaping than the case of blocking shrimp. The bending angles of tail flip between net blocking and passing through mesh were not significantly different while the bending time of shrimp passing through mesh was significantly longer than when shrimp blocking on the net. Accordingly the angular velocity of passing through mesh was significantly slower than blocking on the net although the angular velocity of the tail flip was not significantly related with carapace length. The main feature of tail flip for mesh penetration was considered as smaller diagonal direction as moving and passing angle in relation to net panel as right angle to flow direction rather than the angular velocity of tail flip.

High frequency measurement and characterization of ACF flip chip interconnects

  • 권운성;임명진;백경욱
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.11a
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    • pp.146-150
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    • 2001
  • Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe. And the cascade transmission matrix conversion was performed. The same measurements and conversion techniques were conducted on the assembled test chip and substrate at the same frequency range. Then impedance values in ACF flip-chip interconnection were extracted from cascade transmission matrix. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of SiO$_2$filler to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. High frequency behavior of metal Au stud bumps was investigated. The resonance frequency of the metal stud bump interconnects is higher than that of ACF flip-chip interconnects and is not observed at the microwave frequency band. The extracted model parameters of adhesive flip chip interconnects were analyzed with the considerations of the characteristics of material and the design guideline of ACA flip chip for high frequency applications was provided.

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Optimization of Injection Process Conditions For Control of Weldline Positions on Flip Top Cap (Flip Top Cap의 웰드라인 위치조정을 위한 사출성형조건의 최적화)

  • Seo, Keum-Hee;Song, Byeong-Uk;Cho, Ji-Hyun;Seo, Tae-Il;Lee, Jeong-Won;Shin, Jang-Soon
    • Proceedings of the KAIS Fall Conference
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    • 2011.12b
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    • pp.413-416
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    • 2011
  • Flip top cap은 경량성, 가공성, 내식성 우수하여 최근에 생활 용기 뚜껑으로 많이 활용되고 있다. Flip top cap은 사출성형에 의해 제작 되며 사출성형 과정에서 힌지부분에 웰드라인(Weldline)이 형성되어 기계적 강도가 떨어지게 된다. Flip top cap은 생활용기에 사용되며 실제생활에서 많은 작동을 요구하기 때문에 힌지부분의 웰드라인은 제품불량에 큰 원인이 된다. 또한 Flip top cap은 생산성을 높이기 위해 멀티캐비티(Multi-cavity) 사출방식을 선호한다. 멀티캐비티 방식은 높은 사출압력을 요구하기 때문에 사출품의 불량과 사출기에 많은 부하가 예상된다. 본 연구에서는 게이트 위치를 조정함으로써 사출품 힌지부분에서 발생할 수 있는 웰드라인을 품질에 영향이 없는 곳으로 이동시키고 최적의 사출 압력을 찾기 위한 유동해석을 통해 최적의 사출조건을 도출함으로써 Flip top cap의 기계적 품질과 제품생산성 향상을 위한 연구가 수행되었다.

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A Design of a Ternary Storage Elements Using CMOS Ternary Logic Gates (CMOS 3치 논리 게이트를 이용한 3치 저장 소자 설계)

  • Yoon, Byoung-Hee;Byun, Gi-Young;Kim, Heung-Soo
    • Journal of IKEEE
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    • v.8 no.1 s.14
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    • pp.47-53
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    • 2004
  • We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

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Prediction of the Impact Lifetime for Board-Leveled Flip Chips by Changing the Design Parameters of the Solder Balls (플립칩의 설계변수 변화에 따른 보드레벨 플립칩에서의 낙하충격 수명예측)

  • Lee, Soo Jin;Kim, Seong Keol
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.24 no.1
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    • pp.117-123
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    • 2015
  • The need for drop simulations for board-leveled flip chips in micro-system packaging has been increasing. There have been many studies on flip chips with various solder ball compositions. However, studies on flip chips with Sn-1.0Ag-0.5Cu and Sn-3.0Ag-0.5Cu have rarely been attempted because of the unknown material properties. According to recent studies, drop simulations with these solder ball compositions have proven feasible. In this study, predictions of the impact lifetime by drop simulations are performed considering Cu and Cu/Ni UBMs using LS-DYNA to alter the design parameters of the flip chips, such as thickness of the flip chip and size of the solder ball. It was found that a smaller chip thickness, larger solder ball diameter, and using the Cu/Ni UBM can improve the drop lifetime of solder balls.

Low Power Flip-Flop Circuit with a Minimization of Internal Node Transition (인터널 노드 변환을 최소화시킨 저전력 플립플롭 회로)

  • Hyung-gyu Choi;Su-yeon Yun;Soo-youn Kim;Min-kyu Song
    • Transactions on Semiconductor Engineering
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    • v.1 no.1
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    • pp.14-22
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    • 2023
  • This paper presents a low-power flip-flop(FF) circuit that minimizes the transition of internal nodes by using a dual change-sensing method. The proposed dual change-sensing FF(DCSFF) shows the lowest dynamic power consumption among conventional FFs, when there is no input data transition. From the measured results with 65nm CMOS process, the power consumption has been reduced by 98% and 32%, when the data activity is 0% and 100%, respectively, compared to conventional transmission gate FF(TGFF). Further, compared to change-sensing FF(CSFF), the power consumption of proposed DCSFF is smaller by 30%.

Construction of Mammalian Cell Expression Vector for pAcGFP-bFLIP(L) Fusion Protein and Its Expression in Follicular Granulosa Cells

  • Yang, Run Jun;Li, Wu Feng;Li, Jun Ya;Zhang, Lu Pei;Gao, Xue;Chen, Jin Bao;Xu, Shang Zhong
    • Asian-Australasian Journal of Animal Sciences
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    • v.23 no.3
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    • pp.401-409
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    • 2010
  • FLICE inhibitory protein (FLIP) is one of the important anti-apoptotic proteins in the Fas/FasL apoptotic path which has death effect domains, mimicking the pro-domain of procaspase-8. To reveal the intracellular signal transduction molecules involved in the process of follicular development in the bovine ovary, we cloned the c-FLIP(L) gene in bovine ovary tissue with the reverse transcription polymerase chain reaction (RT-PCR), deleted the termination codon in its cDNA, and directionally cloned the amplified c-FLIP(L) gene into eukaryotic expression vector pAcGFP-Nl, including AcGFP, and successfully constructed the fusion protein recombinant plasmid. After identifying by restrictive enzyme BglII/EcoRI and sequencing, pAcGFP-bFLIP(L) was then transfected into follicular granulosa cells, mediated by Lipofectamine 2000, the expression of AcGFP observed and the transcription and expression of c-FLIP(L) detected by RT-PCR and Western blot. The results showed that the cattle c-FLIP(L) was successfully cloned; the pAcGFPbFLIP(L) fusion protein recombinant plasmid was successfuly constructed by introducing a BglII/EcoRI cloning site at the two ends of the c-FLIP(L) open reading frame and inserting a Kozak sequence before the start codon. AcGFP expression was detected as early as 24 h after transfection. The percentage of AcGFP positive cells reached about 65% after 24 h. A 1,483 bp transcription was amplified by RT-PCR, and a 83 kD target protein was detected by Western blot. Construction of the pAcGFP-bFLIP(L) recombinant plasmid should be helpful for further understanding the mechanism of regulation of c-FLIP(L) on bovine oocyte formation and development.

Adhesive Flip Chip Technology

  • Paik, Kyung-W
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.10a
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    • pp.7-38
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    • 2000
  • Performance, reliability, form factor drive flip chip use. BGAs and CSPs will provide stepping stone to FC DCA .Growing vendor infrastructure - Low cost, high density organic substrates -New generations of fluxes and underfills .Adhesives flip chip technology as a low cost flip chip alternatives -Low cost Au stud or Electroless Ni bumps -Reliable thermal cycling and electrical performance.

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