• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.337-345
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• 2016

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

• 대한금속재료학회지
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• 제50권10호
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• pp.785-792
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• 2012

A new flip chip structure consisting of interlocking joints locally surrounded by non-conductive adhesive was investigated in order to improve the contact resistance characteristics and prevent the parasitic capacitance increase. The average contact resistance of the interlocking joints was substantially reduced from $135m{\Omega}$ to $79m{\Omega}$ by increasing the flip chip bonding pressure from 85 MPa to 185 MPa. Improvement of the contact resistance characteristics at higher bonding pressure was attributed not only to the increased contact area between Cu chip bumps and Sn pads, but also to the severe plastic deformation of Sn pads caused during formation of the interlocking-joint structure. The parasitic capacitance increase due to the non-conductive adhesive locally surrounding the flip chip joints was estimated to be as small as 12.5%.

• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.189-192
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• 2000

We fabricated rapid single-flux-quantum RS flip-flop circuits with and without Y$_1$Ba$_2$Cu$_3$O$_{7-{\delta}}$(YBCO) ground plane. The circuit consists of SNS-type ramp-edge Josephson junctions that have cobalt-doped YBCO and Sr$_2$AITaO$_6$(SAT) for barrier layer and insulator layer, respectively. The fabricated Josephson junction showed a typical RSJ-like current-voltage(I-V) characteristics above 50K. We sucessfuly demonstrated RS flip-flop at temperatures around 50K. The RS flip-flop fabricated on ground plane showed more definite set and reset state in voltage-flux(V-${\phi}$) modulation curve for read SQUID, which may be attributed to a shielding effect of the YBCO ground plane.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• 한국전기전자재료학회논문지
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• 제28권10호
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• pp.676-681
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• 2015

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

• 마이크로전자및패키징학회지
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• 제29권2호
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• pp.49-52
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• 2022

Flip Chip 제품 난이도 증가에 따라 신뢰성 관점에서 안정적인 Package (이하 PKG) 소재 기술에 대한 관심이 점차 높아지는 추세이다. 현재 flip chip PKG의 주요 신뢰성 불량은 Sn bridge와 Cu 확산 이다. 위 2가지 형태 모두 본질적으로는 bump 주변 잔류한 flux residue에 의하여 발생한 미세 공극이 유발하는 불량이다. 이러한 형태의 신뢰성 불량 발생 문제점을 최소화하기 위해 Molded Under-Fill (이하 MUF) 소재의 핵심 조성과 flux 간 상관 관계를 검토하였다. 금번 연구를 통하여 MUF 소재의 main 구성 요소인 base resin, filler와 flux에 대한 상관 관계를 정의 하였으며, 이러한 lesson learn을 토대로 flux immunity가 개선된 MUF 소재 조성을 설계할 수 있었다. 현재 해당 소재 조성으로 흡습 신뢰성 85%/85%/24hrs 확보와 파괴 분석으로 bump 주변 미세 공극의 미 발생을 확인 하였다. 본 연구 결과는 양산 단계에서의 flip chip 공정 수율 향상과 MUF와 flux 간 상용성 연구에 대한 이해를 돕는데 기여할 것으로 예상된다.

• Journal of Welding and Joining
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• 제26권3호
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• pp.30-36
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• 2008

A flip-chip bonding system using IR laser with a wavelength of 1064 nm was developed and associated process parameters were analyzed using Taguchi methods. An infrared laser beam is designed to transmit through a silicon chip and used for transferring laser energy directly to micro-bumps. This process has several advantages: minimized heat affect zone, fast bonding and good reliability in the microchip bonding interface. Approximately 50 % of the irradiated energy can be directly used for bonding the solder bumps with a few seconds of bonding time. A flip-chip with 120 solder bumps was used for this experiment and the composition of the solder bump was Sn3.0Ag0.5Cu. The main processing parameters for IR laser flip-chip bonding were laser power, scanning speed, a spot size and UBM thickness. Taguchi methods were applied for optimizing these four main processing parameters. The optimized bump shape and its shear force were modeled and the experimental results were compared with them. The analysis results indicate that the bump shape and its shear force are dominantly influenced by laser power and scanning speed over a laser spot size. In addition, various effects of processing parameters for IR laser flip-chip bonding are presented and discussed.

• 마이크로전자및패키징학회지
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• 제22권3호
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• pp.39-44
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• 2015

이방성 전도접착제를 이용하여 Cu/Au 칩 범프를 Cu 기판 배선에 플립칩 실장한 접속부에 대해 CNT-Ag 복합패드가 접속저항에 미치는 영향을 연구하였다. CNT-Ag 복합패드가 내재된 플립칩 접속부가 CNT-Ag 복합패드가 없는 접속부에 비해 더 낮은 접속저항을 나타내었다. 각기 25 MPa, 50 MPa 및 100 MPa의 본딩압력에서 CNT-Ag 복합패드가 내재된 접속부는 $164m{\Omega}$, $141m{\Omega}$ 및 $132m{\Omega}$의 평균 접속저항을 나타내었으며, CNT-Ag 복합패드를 형성하지 않은 접속부는 $200m{\Omega}$, $150m{\Omega}$ 및 $140m{\Omega}$의 평균 접속저항을 나타내었다.

• 한국융합학회논문지
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• 제9권6호
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• pp.209-215
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• 2018

대학 교양수학은 이공계열에서 필수 과목으로 개설하고 있으나 성취도가 낮은 학생들은 학습에 어려움을 느끼고 있어 대안으로 자기 주도와 학습자 중심으로 효과성이 높은 교수법으로 잘 알려진 플립러닝이 제시되고 있다. 그러나 이 교수법에서도 몇 가지 문제점들이 지적되고 있어 플립러닝에 대한 대안적 방법으로 PBL을 플립러닝에 적용한 플립 PBL 수업을 교양수학 과목에 적용하여 기존 플립러닝 수업의 문제점을 보완하고 수학에 대한 흥미를 높일 수 있는지의 효과성을 알아보고자 한다. 본 연구에서는 플립 PBL 수업을 적용한 실험집단과 기존 플립러닝 수업을 적용한 통제집단의 비교연구에서의 교육적 효과성을 알아본 결과 첫째, 지필고사 결과에서는 실험집단이 통제집단보다 평균이 22점 이상 높게 나타나 학업성취도 향상에 효과가 있는 것으로 나타났고 둘째, 성찰저널 분석에서는 통제집단과 대조적으로 실험집단에서 수학의 흥미도 향상에 대한 긍정적인 내용이 많아 흥미도 변화에도 긍정적 효과가 나타나 이교수법이 기존의 플립러닝을 보완할 수 있는 교수법으로 확대 적용되기를 기대한다.