• Title/Summary/Keyword: flatband voltage shift

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A study of properties which the diffusion barrier Ta and IMD(Inter-Metal Dielectric) metrial SiOCH for $Cu^+$ ion diffusion (구리이온의 확산에 대한 IMD(Inter-Metal Dielectric)용 Low-k 물질인 SiOCH와 diffusion barrier Ta의 특성에 관한 연구)

  • Kim, J.W.;Song, J.H.;Choi, Y.H.;Kim, J.G.;Lee, H.Y.
    • Proceedings of the KIEE Conference
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    • 2004.07c
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    • pp.1697-1699
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    • 2004
  • In this investigation, we have studied the diffusion of the $Cu^+$ ion in the Cu/Ta/SiOCH/Si and Cu/Ta/$SiO_2$/Si MIS-C structure. The Cu ions diffusion into the Ta barrier and SiOCH was examined by shift in flatband voltage of capacitance-voltage measurement and leakage current of current-voltage measurement. These evalution indicated that $Cu^+$ ion diffusion rate in Ta/SiOCH is considerably lower then the Ta/$SiO_2$ structure. And diffusion barrier Ta(50[nm]) is useful barrier against $Cu^+$ ion diffusion up to 450$^{\circ}C$.

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Electrical Characteristics of Carbon Nanotube Embedded 4H-SiC MOS Capacitors (탄소나노튜브를 첨가한 4H-SiC MOS 캐패시터의 전기적 특성)

  • Lee, Taeseop;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.9
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    • pp.547-550
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    • 2014
  • In this study, the electrical characteristics of the nickel (Ni)/carbon nanotube (CNT)/$SiO_2$ structures were investigated in order to analyze the mechanism of CNT in MOS device structures. We fabricated 4H-SiC MOS capacitors with or without CNTs. CNT was dispersed by isopropyl alcohol. The capacitance-voltage (C-V) and current-voltage (I-V) are characterized. Both devices were measured by Keithley 4200 SCS. The experimental flatband voltage ($V_{FB}$) shift was positive. Near-interface trap charge density ($N_{it}$) and negative oxide trap charge density ($N_{ox}$) value of CNT embedded MOS capacitors was less than that values of reference samples. Also, the leakage current of CNT embedded MOS capacitors is higher than reference samples. It has been found that its oxide quality is related to charge carriers and/or defect states in the interface of MOS capacitors.

A study on the fabrication and characteristics of the scaled MONOS nonvolatile memory devices for low voltage EEPROMs (저전압 EEPROM을 위한 Scaled MONOS 비휘발성 기억소자의 제작 및 특성에 관한 연구)

  • 이상배;이상은;서광열
    • Electrical & Electronic Materials
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    • v.8 no.6
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    • pp.727-736
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    • 1995
  • This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

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Use of a capacitance voltage technique to study copper drift diffusion in low-k polyimide (C-V Technique을 이용한 low-k polyimide로의 구리의 drift diffusion 연구)

  • Choi, Yong-Ho;Lee, Heon-Yong;Kim, Jee-Gyun;Kim, Jung-Woo;Kim, Yoo-Kyuong;Park, Jin-Ho
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.05c
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    • pp.137-140
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    • 2003
  • Cu+ ions drift diffusion in different dielectric materials is evaluated. The diffusion is investigated by measuring shift in the flatband voltage of capacitance/voltage measurements on Cu gate capacitors after bias temperature stressing. At a field of 1.lMV/cm and temperature $200^{\circ}C$, $250^{\circ}C$, $300^{\circ}C$ for 1H, 2H, 5H. The Cu+ ions drift rate of polyimide$(2.8{\leq}k{\leq}3.2)$ is considerably lower than thermal oxide. Also Cu+ drift rate of polyimide is similar to PECVD oxide. But, polyimide film is even more resistant to Cu drift diffusion and thermal effect than Thermal oxide, PECVD oxide: This results got a comparative reference. The important conclusion is that polyimide film is strongly dielectric material by thermal effect and Cu drift diffusion.

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Rapid Thermal Nitridation of $SiO_2$ (급속 열처리에 의한 $SiO_2$ 의 질화)

  • 이용현;왕진석
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.5
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    • pp.709-715
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    • 1990
  • SiO2 films were nitrided by tungsten-halogen heated rapid thermal annealing in ammonia gas at temperatures of 900-1100\ulcorner for 15-180sec. The nitroxide films were analyzed using Auger electron spectroscopy. MIS caapcitors were fabricated using these films as gate insulators. I-V and C-V characteristics of MIS capacitors were investigated. The AES depth profiles of nitroxide film show that the nitrogen rich layer is, at the early stage of nitridation, formed at the surface of nitroxide film and near the interface between nitroxide and silicon. Nitridation of SiO2 makes the film have a larger effective average refractive index. The thermal nitridation of SiO2 on silicon causes the flatband voltage shift due to the change of the fixed charge density. It is found that the dominant conduction mechanism in nitroxide is Fowler-Nordheim tunneling. Rapid thermal nitridation of 200\ulcornerSiO2 on silicon results in an improvement in the dielectric breakdown electric field.

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Plasma Etching Damage of High-k Dielectric Layer of MIS Capacitor (High-k 유전박막 MIS 커패시터의 플라즈마 etching damage에 대한 연구)

  • 양승국;송호영;오범환;이승걸;이일항;박새근
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1045-1048
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    • 2003
  • In this paper, we studied plasma damage of MIS capacitor with $Al_2$O$_3$ dielectric film. Using capacitor pattern with the same area but different perimeters, we tried to separate etching damage mechanism and to optimize the dry etching process. After etching both metal and dielectric layer by the same condition, leakage current and C-V measurements were carried out for Pt/A1$_2$O$_3$/Si structures. The flatband voltage shift was appeared in the C-V plot, and it was caused by the variation of the fixed interface charge and the interface trapped charge. From I-V measurement, it was found the leakage current along the periphery could not be ignored. Finally, we established the process condition of RF power 300W, 100mTorr, Ar/Cl$_2$ gas 60sccm as an optimal etching condition.

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A Study on the Electrical Characteristics of Poly-Si Gate MOS Devices (다결정 실리콘을 게이트로 이용한 MOS 소자의 전기적 특성에 관한 연구)

  • 이오성;윤돈영;김상용;장의구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1988.10a
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    • pp.79-81
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    • 1988
  • The capacitance-voltage (C-V) characteristics of poly-Si gate MOS devices fabricated by Low-Pressure Chemical Vapor Deposition (LPCVD) system have been studied. In the case poly-Si gate, work function difference and surface state charge density was found lower than that of Al gate. This fact was identified from the C-V curves that flatband shift was shown small due to the hydrogen gas diffused into oxide in processing of alloy and the annealing effect in processing of poly-Si deposition.

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The oxidation of silicon nitride layer (실리콘 질화막의 산화)

  • 정양희;이영선;박영걸
    • Electrical & Electronic Materials
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    • v.7 no.3
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    • pp.231-235
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    • 1994
  • The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

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Dielectric properties of TEX>$Al_2O_3$ thin Elm deposited at room temperature by DC reactive sputtering (DC 반응성 스퍼터링으로 상온에서 증착한 $Al_2O_3$ 박막의 유전특성)

  • 박주동;최재훈;오태성
    • Journal of the Korean Vacuum Society
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    • v.9 no.4
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    • pp.411-418
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    • 2000
  • $Al_2O_3$ thin films of 300 nm thickness were deposited at room temperature using DC reactive sputtering with variation of the $O_2$ content in the sputtering gas from 30% to 70%. Regardless of the $O_2$ content in the sputtering gas, the sputtered $Al_2O_3$ films were amorphous and exhibited the refractive index of 1.58. When the $O_2$ content in the sputtering gas was higher than 50%, the $Al_2O_3$ films exhibited excellent transmittance of about 98% at 550 nm wavelength. However, the transmittance decreased to about 94% for the $Al_2O_3$ films deposited with the sputtering gas of the 30% and 40% $O_2$contents. The optimum dielectric properties (dielectric constant of 10.9 and loss tangent of 0.01) was obtained for the $Al_2O_3$ film deposited with the sputtering gas of the 50% $O_2$ content. When the $O_2$ content in the sputtering gas was within 40% to 60%, the $Al_2O_3$ films exhibited no shift of flatband voltage $V_{FB}$ in C-V curves and exhibited leakage current density lower than $10^{-5}\textrm{A/cm}^2$ at 150 kV/cm.

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Electrical properties of metal-oxide-semiconductor structures containing Si nanocrystals fabricated by rapid thermal oxidation process (급속열처리산화법으로 형성시킨 $SiO_2$/나노결정 Si의 전기적 특성 연구)

  • Kim, Yong;Park, Kyung-Hwa;Jung, Tae-Hoon;Park, Hong-Jun;Lee, Jae-Yeol;Choi, Won-Chul;Kim, Eun-Kyu
    • Journal of the Korean Vacuum Society
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    • v.10 no.1
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    • pp.44-50
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    • 2001
  • Metal oxide semiconductor (MOS) structures containing nanocrystals are fabricated by using rapid thermal oxidations of amorphous silicon films. The amorphous films are deposited either by electron beam deposition method or by electron beam deposition assisted by Ar ion beam during deposition. Post oxidation of e-beam deposited film results in relatively small hysteresis of capacitance-voltage (C-V) and the flat band voltage shift, $\DeltaV_{FB}$ is less than 1V indicative of the formation of low density nanocrystals in $SiO_2$ near $SiO_2$/Si interface. By contrast, we observe very large hysteresis in C-V characteristics for oxidized ion-beam assisted e-beam deposited sample. The flat band voltage shift is larger than 22V and the hysteresis becomes even broader as increasing injection times of holes at accumulation condition and electrons at inversion condition. The result indicates the formation of slow traps in $SiO_2$ near $SiO_2$/Si interface which might be related to large density nanocrystals. Roughly estimated trap density is $1{\times}10^{13}cm^{-2}$. Such a large hysteresis may be explained in terms of the activation of adatom migration by Ar ion during deposition. The activated migration may increase nucleation rate of Si nuclei in amorphous Si matrix. During post oxidation process, nuclei grow into nanocrystals. Therefore, ion beam assistance during deposition may be very feasible for MOS structure containing nanocrystals with large density which is a basic building block for single electron memory device.

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