• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Korean Society of Systems Engineering
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• v.13 no.2
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• pp.9-17
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• 2017

Concept development of a real-time Field Programmable Gate Array (FPGA)-based switched Ethernet data communication network for the Man-Machine Interface System (MMIS) is presented in this paper. The proposed design discussed in this research is based on the systems engineering (SE) approach. The design methodology is effectively developed by defining the concept development stage of the life-cycle model consisting of three successive phases, which are developed and discussed: needs analysis; concept exploration; and concept definition. This life-cycle model is used to develop an FPGA-based time-triggered Ethernet (TTE) switched data communication network for the non-safety division of MMIS system to provide real-time data transfer from the safety control systems to the non-safety division of MMIS and between the non-safety systems including control, monitoring, and information display systems. The original IEEE standard 802.3 Ethernet networks were not typically designed or implemented for providing real-time data transmission, however implementing a network that provides both real-time and on-demand data transmission is achievable using the real-time Ethernet technology. To develop the design effectively, context diagrams are implied. Conformance to the stakeholders needs, system requirements, and relevant codes and standards together with utilizing the TTE technology are used to analyze, synthesize, and develop the MMIS non-safety data communication network of the APR1400 nuclear power plant.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.9
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• pp.124-129
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• 2009

Recently, PWM inverter is widely utilized for many industrial applications such as high performance drive and space vector pulse width modulation(SVPWM) inverter which has high voltage ratio and low harmonics compared to conventional PWM inverter. This paper presents the implementation on a field programmable gate array(FPGA) of a SVPWM module for a voltage source inverter. The SVPWM module consists of PWM generator, current and position sensor interface and dead time compensator. The implemented SVPWM module can be integrated with a digital signal processor(DSP) to provide a flexible and effective solution for high performance voltage source inverter and for the use of multi-motor control. The performance of SVPWM module is verified by simulation and several experimental results.

• Journal of IKEEE
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• v.23 no.4
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• pp.1400-1407
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• 2019

In this paper, we propose a support vector machine (SVM) based gas classifier that can support real-time self-learning. The modified sequential minimal optimization (MSMO) algorithm is employed to train the proposed SVM. By using a shared structure for learning and classification, the proposed SVM reduced the hardware area by 35% compared to the existing architecture. Our system was implemented with 3,337 CLB (configurable logic block) LUTs (look-up table) with Xilinx Zynq UltraScale+ FPGA (field programmable gate array) and verified that it can operate at the clock frequency of 108MHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.6
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• pp.2201-2216
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• 2015

Peak to average power ratio (PAPR) is one of the main imperfections in the broadband communication systems with multiple carriers. In this paper, a new crest factor reduction (CFR) scheme based on interleaved phase sequence called Dummy Sequence Insertion Enhanced Partial Transmit Sequence (DSI-EPTS) is proposed which effectively reduces the PAPR while at the same time keeps the total complexity low. Moreover, the prototype of the proposed scheme in field programmable gate array (FPGA) is demonstrated. In DSI-EPTS scheme, a new matrix of phase sequence is defined which leads to a significant reduction in hardware complexity due to its less searching operation to extract the optimum phase sequence. The obtained results show comparable performance with slight difference due to the FPGA constraints. The results show 5 dB reduction in PAPR by applying the DSI-EPTS scheme with low complexity and low power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1777-1781
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• 2011

Tosin backplane system design of this study (Backplane) from the HSTL (High-Speed Transceiver Logic) characteristics of the transmit and receive data using the HSPICE simulations and the actual implementation on the FPGA Data transmission characteristics were described by comparing the simulation results. Simulation and measurement criteria for point to point data transmission characteristics of wire length possible to send and receive data about the speed limits were reviewed. Measured point to point connection to send and receive signals at terminal velocity, the factors that affect the electrical noise around the wire length and showed a very important role.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.83-90
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• 2004

This paper describes on-board decentralized data acquisition system that acquires and encodes the numerous sensor data distributed on the big flight vehicles efficiently. The system's sub-units which have one encoder unit and several remote units were designed and simulated according to the communication protocols and the control, sequence logics based on the FPGA chip. And we have made the functional verification of the acquisition, collection and formatting of remote analog and digital data for the manufactured hardwares.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.3
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• pp.110-117
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• 2014

This paper reports a depth-adaptive sharpness adjustment algorithm for stereoscopic perception improvement, and presents its field-programmable gate array (FPGA) implementation results. The first step of the proposed algorithm was to estimate the depth information of an input stereo video on a block basis. Second, the objects in the input video were segmented according to their depths. Third, the sharpness of the foreground objects was enhanced and that of the background was maintained or weakened. This paper proposes a new sharpness enhancement algorithm to suppress visually annoying artifacts, such as jagging and halos. The simulation results show that the proposed algorithm can improve stereoscopic perception without intentional depth adjustments. In addition, the hardware architecture of the proposed algorithm was designed and implemented on a general-purpose FPGA board. Real-time processing for full high-definition stereo videos was accomplished using 30,278 look-up tables, 24,553 registers, and 1,794,297 bits of memory at an operating frequency of 200MHz.

• ETRI Journal
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• v.33 no.5
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• pp.731-740
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• 2011

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of- the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.