• 한국진공학회지
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• 제2권3호
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• pp.335-338
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• 1993

텅스텐으로 만들어진 field emitter와 탄소로 만들어진 field emitter에서 생기는 step이나 spike 형태의 잡음에 대하여 비교 연구하였다. 그리고 dispenser 형태의 field emiter와 array 형태의 field emitter와 같은 새로운 형태의 field emitter를 설명하였다.

• 한국추진공학회:학술대회논문집
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• 한국추진공학회 2004년도 제22회 춘계학술대회논문집
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• pp.300-305
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• 2004

A preliminary study on. field emitter array cathodes was conducted aiming at applying for electrodymanic tether (EDT) propulsion systems. The EDT propulsion systems are assumed to use for active removal systems of post-mission spacecraft, which would otherwise become space debris. A survey on field emit-ter array cathode technology was conducted, and it showed that carbon nanotube (CNT) emitters are suit-able to EDT application. Trial fabrications and evaluation tests of CNT emitters were conducted, which demonstrated a target emission current density of 10 ㎃/$\textrm{cm}^2$. It was found out that the most important technical issue for developing CNT emitters is to improve the performance against voltage breakdown between the emitter and the opposite electrode.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.59-63
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• 2000

For the Mo-tip field emitter array, the method by which the geometrical structure of the gate insulator wall could be modified in order to improve field emission properties(turn-on voltage and gate leakage current). The device having a gate insulator of complex shape, which means the combined geometrical structure with round shape made by wet etching and vertical shape made by dry etching processes, was fabricated and the field emission properties of the three kinds of devices were compared. As a result, the electric field applied to tip apex could be increased and gate leakage current could be decreased by employing the gate insulator having geometrical wall structure of mixed shape. Finally, the obtained empirical results were analyzed by simulation of electric field distribution at/near the tip apex and gate insulator using SNU-FEAT simulator.

• 한국진공학회지
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• 제2권3호
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• pp.331-334
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• 1993

여러 종류의 수직 또는 수평 형태의 field emitter array가 연구되었다. 그 중 수평형의 FEA는 emitter가 동일 평면 위에 구성되어 있고, gate는 고주파의 응용을 위하여서는 더욱 적합하다. 이 빗살 모양의 FEA의 구조, emission 성질, 응용에 대하여 설명한다.

• Transactions on Electrical and Electronic Materials
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• 제3권1호
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• 전자공학회논문지D
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• 제34D권4호
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• pp.100-105
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• 1997

3-dimensional finite element mehtod (FEM) elecrical field analysis was performed to obtain electric fields on a field emission display (FED) tip in an array form. Because, unlike a single tip structure, there is no azimuthal symmetry for a tip aary, 3D analysis is necessary. To reduce memory requriement the simulatio was performed by applying the neumann boundary condition to the intermediate plane between tips to take the effect of the array on the electric field into account and corresponding current was calculated. To verify our algorithm, comparison between simulation resutls and experimental data from another paper was made and the difference was discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.347-350
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• 2001

A typical Mold method is to form a gate electrode, a gate oxide, and emitter tip after fabrication of mold shape using wet-etching of Si substrate. In this study, however, new Mold method using a side wall space structure is used in order to make sharper emitter tip with a gate electrode. Using LPCVD(low pressure chemical vapor deposition), a gate oxide and electrode layer are formed on a Si substrate, and then BPSG(Boro phospher silicate glass) thin film is deposited. After, the BPSG thin film is flowed into a mold as high temperature in order to form a sharp mold structure. Next TiN thin film is deposited as a emitter tip substance. The unfinished device with a glass substrate is bonded by anodic bonding techniques to transfer the emitters to a glass substrate, and Si substrate is etched using KOH-deionized water solution. Finally, we made sharp field emitter array with gate electrode on the glass substrate.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1997년도 제13회 학술발표회 논문개요집
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• pp.89-90
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• 1997

• 한국재료학회:학술대회논문집
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• 한국재료학회 2000년도 추계학술발표강연 및 논문개요집
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• pp.85-85
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• 2000

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권7호
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• pp.525-529
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• 1999

The influence of ambient gases on field emission performance of Mo-field emitter array(FEA) in the frit-sealing step of field emission display(FED) packaging process was investigated. Mo-tip FEA was mounted on the glass substrate having a surrounded frit(Ferro FX11-137) and fired at $415^{\circ}C$ in the ambient gases of air, $N_2$ and Ar. The Ar gas was proved to be most proper ambient among the used gases through evaluating the turn-on voltage and field emission current of the fired Mo-tip FEA devices. It was confirmed that the Mo surface fired in Ar ambient was less oxidized when compared with another ones annealed in air and Ar ambient by the AFM, XPS, AES and SIMS analysis. Finally, the 3.5 inch-sized Mo-tip FED, which was packaged using frit-sealing process in the Ar ambient, was proposed.