• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.43-51
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• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• ETRI Journal
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• v.36 no.6
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• pp.1066-1069
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• 2014

We propose a lane adaptive recovery scheme for multiple lane faults in a multi-lane-based Ethernet link. In our scheme, when lane faults occur in a link, they are processed not as full link faults but as partial link faults. Our scheme provides a higher link utilization and lower packet loss rate by reusing the available lanes of the link and providing a low recovery time of under a microsecond.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.99-109
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• 1992

First, the coupling faults of semiconductor memory are classified in detail. The chained coupling fault is introduced and defined, which results from sequential influencing of the coupling effects among memory cells, and its mapping relation is described. The linked coupling fault and its order are defined. Second, the deterministic “Algorithm GA” is proposed, which detects stuack-at faults, transition faults, address decoder faults, unlinked 2-coupling faults, and unlinked chained coupling faults. The time complexity and the fault coverage are improved in this algorithm. Third, it is proved that the march test of an address sequence can detect 97.796% of the linked 2-coupling faults with order 2. The deterministic “Algorithm NA” proposed can detect to the limit. The time complexity and the fault coverage are improved in this algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2453-2461
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• 2009

Faults caused by medium-voltage customers have been increased and enlarged their portion in total distribution faults even though we have done many efforts. In the previous paper, we suggested the fault prediction model and fault prevention method for these distribution line faults. However we can't directly apply this prediction model in the field. Because we don't have an useful program to predict those customers causing distribution line faults. This paper presents the construction method of data warehouse in ERP system and the program to find customers who cause distribution line faults in medium-voltage customer's electric facility management applying data mining techniques. We expect that this data warehouse and prediction program can effectively reduce faults resulted from medium-voltage customer facility.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.801-803
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• 2003

Faults in induction motors can be categorized into mechanical faults and electrical faults, and most mechanical faults result from inferiority or damage of the bearing, while most electrical faults derive from insulation faults of stator windings and rotor bar cracks. When a crack appears on the rotor bar, its efficiency decreases, which increases energy consumption and temperature, reducing the life span of the motor. This kind of fault can only be sensed by the protection relay after the condition has worsened to a certain degree, bringing massive economic loss. This paper will deal with the diagnosis method of rotor bar faults through the load current analysis method of the motor used during operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.74-84
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• 2003

Conventional test algorithms do not effectively detect faults by word-line and bit-line coupling noise resulting from the increase of the density of memories. In this paper, the possibility of faults caused by word-line coupling noise is shown, and new fault model, WLSFs(Word-Line Sensitive Fault) is proposed. We also introduce the algorithm considering both word-line and bit-line coupling noise simultaneously. The algorithm increases probability of faults which means improved fault coverage and more effective test algorithm, compared to conventional ones. The proposed algorithm can also cover conventional basic faults which are stuck-at faults, transition faults and coupling faults within a five-cell physical neighborhood.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.8
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• pp.405-411
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• 2000

When faults occur in transmission lines, the classification of faults is very important. If the fault is HIF(High Impedance Fault), it cannot be detected or removed by conventional overcurrent relays (OCRs), and results in fire hazards and causes damages in electrical equipment or personal threat. The fast discrimination of fault needs to effective protection and treatment and is important problem for power system protection. This paper propolsed the fault detection and discrimination algorithm for LIFs(Low Impedance Faults) and HIFs(High Impedance Faults). This algorithm uses artificial neural networks and variation of 3-phase maximum currents per period while faults. A double lines-to-ground and line-to-line faults can be detected using Neural Network. Also, the other faults can be detected using the value of variation of maximum current. Test results show that the proposed algorithms discriminate LIFs and HIFs accurately within a half cycle.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.59-62
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• 2000

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11b
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• pp.200-203
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• 2005

Ball bearings not only sustain the system, but permit the rotational component to rotate. Excessive radial or axial load and many other reasons can cause faults to be created and grown rapidly in each component. The grown faults make noise and vibration, which can make the system unstable. Therefore, it is important to detect faults as early as possible. For this reason, there have been many researches on fault detection method of early faults in a ball bearing. The fault defection methods can be categorized to several groups by signal processing methods. Not all the methods are efficient for finding early faults. We select representative methods known as efficient for detecting early faults and compare the results for inspecting which method is effective.