• 전자공학회논문지A
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• 제33A권3호
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• 방사성폐기물학회지
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• 제19권4호
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• pp.533-546
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• 2021

Large earthquakes with (M_W > ~ 6) result in ground shaking, surface ruptures, and permanent deformation with displacement. The earthquakes would damage important facilities and infrastructure such as large industrial establishments, nuclear power plants, and waste disposal sites. In particular, earthquake ruptures associated with large earthquakes can affect geological and engineered barriers such as deep geological repositories that are used for storing hazardous radioactive wastes. Earthquake-driven faults and surface ruptures exhibit various fault zone structural characteristics such as direction of earthquake propagation and rupture and asymmetric displacement patterns. Therefore, estimating the respect distances and hazardous areas has been challenging. We propose that considering multiple parameters, such as fault types, distribution, scale, activity, linkage patterns, damage zones, and respect distances, enable accurate identification of the sites for deep geological repositories and important facilities. This information would enable earthquake hazard assessment and lower earthquake-resulted hazards in potential earthquake-prone areas.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.194-196
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• 2005

The command processor in satellite handles the capability of the process of command transmitted from ground station and deliver the processed data to on board computer in satellite. The command processor is consisted of redundant box to increase the reliability and availability of the capability. At each command processor, the processing time of each command processor is different, so the mismatch of processing time makes it difficult to timely synchronize the reception to on board computer and even will be became worse under the command processor's fault. To minimize the tine loss induced by the command processor's fault on board computer must analyze the time distribution of command propagation. This paper presents the logic of minimizing the delay error of command propagation the logic of analyzing the output of command processor.

• 전자공학회논문지C
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• 제34C권8호
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• pp.39-48
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• 1997

The fast redundancy identification is required to perform an efficient test pattern genration. Due to the reconvergent fanouts which make the dependency among objectives and the fault propagation blocking, there may exist redundnat faults in the cirucit. This paper presents the isomorphism identification and the pseudo dominator algorithms which are useful to identify redundant faults in combinational circuits. The isomorphism identification algorithm determines whether mandatory objectives required for fault detection cannot be simultaneously satisfied from primary input assignments or not using binary decision diagrma. The pseudo dominator algorithm determines whether faults propagation is possible or not by considering all paths at a given fanout node. Several experiments using ISCAS 85 benchmark circuits demonstrate the efficiency and practicability of the algorithms.

• Journal of the Optical Society of Korea
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• 제13권1호
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• pp.98-106
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• 2009

This paper proposes an optical wireless transfer agent method which realizes the continuous and swift data transfer of optical wireless terminals in optical wireless networks. The unguided wireless channel generally shows frequent link disconnections and propagation delays due to weak wireless links. Specially speaking, optical wireless channels have more vulnerable links and roaming propagation delays relative to the weakness of the previous RF channels due to their low signal connectivity and small geographic coverage. Conventional optical wireless network protocols did not consider any fault models about physical link faults. Consequently, they have shown data transfer inefficiency for both data link control and physical wireless link control. To overcome these optical wireless environmental problems, this paper suggests a new wireless access point (or base station) agent system, which provides wireless or mobile clients with previous link layer protocols compensated.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 방전 플라즈마 유기절연재료 초전도 자성체연구회
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• pp.169-172
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• 2004

We present the basic properties of a superconducting current limiting fuse (SCLF) based on YBCO/Au films. The SCLFs consists of YBCO stripes covered with Au layers for current shunt. Under the source voltage of 100 $V_{rms}$, the longer the duration time of fault current was, the shorter its discharge time was. The duration time of fault current and its discharge time were reduced by increased voltages in the range of 200 - 300 $V_{rms}$. We thought that this was because the quench propagation was limited by local melting generated with higher voltage.

• 한국지진공학회논문집
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• 제18권3호
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• pp.151-160
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• 2014

Probabilistic tsunami hazard analysis (PTHA) is based on the approach of probabilistic seismic hazard analysis (PSHA) which is performed using various seismotectonic models and ground-motion prediction equations. The major difference between PTHA and PSHA is that PTHA requires the wave parameters of tsunami. The wave parameters can be estimated from tsunami propagation analysis. Therefore, a tsunami simulation analysis was conducted for the purpose of evaluating the wave parameters required for the PTHA of Uljin nuclear power plant (NPP) site. The tsunamigenic fault sources in the western part of Japan were chosen for the analysis. The wave heights for 80 rupture scenarios were numerically simulated. The synthetic tsunami waveforms were obtained around the Uljin NPP site. The results show that the wave heights are closely related with the location of the fault sources and the associated potential earthquake magnitudes. These wave parameters can be used as input data for the future PTHA study of the Uljin NPP site.

• Nuclear Engineering and Technology
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• 제50권4호
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• pp.599-605
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• 2018

Fault diagnosis depends critically on the selection of sensors monitoring crucial process variables. Boolean network (BN) is composed of nodes and directed edges, where the node state is quantized to the Boolean values of True or False and is determined by the logical functions of the network parameters and the states of other nodes with edges directed to this node. Since BN can describe the fault propagation in a sensor network, it can be applied to propose sensor selection strategy for fault diagnosis. In this article, a sufficient condition for parameter identifiability of BN is first proposed, based on which the sufficient condition for fault identifiability of a sensor network is given. Then, the fault identifiability condition induces a sensor selection strategy for sensor selection. Finally, the theoretical result is applied to the fault diagnosis-oriented sensor selection for a nuclear heating reactor plant, and both the numerical computation and simulation results verify the feasibility of the newly built BN-based sensor selection strategy.

• 전자공학회논문지A
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• 제31A권6호
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• pp.169-176
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• 1994

본 논문에서는 조합회로에 있어서 고장 시뮬레이션의 고속화를 위한 효율적인 병렬 평가 알고리듬을 제안한다. 제안한 알고리듬은 고장소자의 평가 및 전파에 있어서 병렬법, 연역법 그리고 동시법의 장점을 이용하고 있기 때문에 시뮬레이션의 고속화를 실현할 수 있을 뿐만 아니라 다치(multi-valued) 신호를 쉽게 취급할 수 있다. 또한, 동일한 신호선에서 발생하는 액티브(active)고장을 동일한 고장 그룹으로 할당하므로써 병렬연산의 효율을 증가시키기 위한 고장의 그룹화(fault grouping) 방법을 제안한다. 제안한 알고리듬은 C언어로 구현하였으며, ISCAS '85 Benchmark 회로에 대한 실험 결과 종래의 동시법과 비교하여 약 2.6배에서 8.2배 정도의 고속화가 실현되었다.

• 대한전자공학회논문지
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• 제17권4호
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• pp.31-37
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• 1980

본 논문은 조합논리회로의 고장검출에 관한 것이다. 회로내의 각 line의 test set사이의 관계를 고찰하므로서 모든 test set을 D-algorithm을 반복하여 적용하지 않고 어느 하나의 test set 만을 구하여 이를 전파시켜서 구할 수 있는 방법을 연구하였고, 두번째로는 모든 선마다의 test set을 구하여 이를 회로에 모두 인가하여 고장을 검출하는 종래의 방법을 벗어나서 입력수만큼의 test set을 인가하여 출력의 상고를 점검하여 고장을 검출하는 방법을 제시되었다.