• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.1
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• pp.35-40
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• 2015

Generators are the most complex and expensive single element in a power system. The generator protection relays should to minimize damage during fault states and must be designed for maximum reliability. A conventional CDR(Current Differential Relaying) technique based on DFT(Discrete Fourier Transform) filter have the disadvantages that the time information can lead to loss in the process of converting the signal from the time domain to the frequency domain. A WT(Wavelet transform) and WT analysis is known that it is possible with the local analysis of the fault and transient signal. In this paper, to overcome the defects in the DFT process, an application of WT for fault detection of generator is presented. This paper describes an selection of mother Wavelet to detect faults of generator. Using collected data from the fault simulation with ATPdraw, we analyzed the several mother Wavelet through the course of MLD(multi-level decomposition) using MATLAB software. Finally, it can be seen that the proposed technique using detail coefficient of Daubechies level 2 which can be fault discriminant of generator.

• Journal of Internet Computing and Services
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• v.9 no.5
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• pp.185-193
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• 2008

An MTBF(mean time between failures) of large scale parallel systems is known to be only an order of several hours, and large computations sometimes result in a waste of huge amount of CPU time, However. the MPI(Message Passing Interface), a de facto standard for message passing parallel programming, suggests no possibility to handle such a problem. In this paper, we propose an application-level fault tolerant computation system, purely on the basis of the current MPI standard without using any non-standard fault tolerant MPI library, that can be used for general scientific synchronous parallel computation.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.421-426
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• 2005

In a large scale parallel computation, some processor or communication link failure results in a waste of huge amount of CPU hours. However, MPI in its current specification gives the user no possibility to handle such a problem. In this paper, we propose an application-level fault tolerant linear system solver by using an MPMD-type asynchronous iteration, purely on the basis of the MPI standard without using any non-standard fault-tolerant MPI library.

• Progress in Superconductivity and Cryogenics
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• v.14 no.3
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• pp.13-17
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• 2012

KEPCO Research Institute has been researching a Superconducting Fault Current Limiter (SFCL) which is considered one of solutions of fault current problems with Korea Institute of Machinery & Materials (KIMM) and Hanyang University since 2011. In this paper, we fabricated a current limiting module and conducted electrical short circuit tests for checking the validity of the transmission level SFCL design. Based on the short circuit characteristics of the second generation High Temperature Superconductor (HTS), we analyzed the short circuit characteristics of 3 parallel connected superconducting wires. The structure of the HTS wire is as follows: the stainless steel stabilizer of $100{\mu}m$ is laminated on the superconductor layer and under the substrate, both of which are electrically jointed with solder. We fabricated the current limiting module which has 40 series and 6 parallel connections and studied the short circuit characteristics of the module under various voltage levels.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.73-77
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• 1990

In this paper we describe the solid-state ac-circuit breaker which has the characteristic of both a half cycle circuit breaker and a current limiting circuit breaker. This circuit breaker has a current limiting resistor in order to surprises the fault current to a certain level and discharge the energe included in circuit inductor. We explain the effect of circuit parameter on transient phenomena of switch device by using EMTP and finally design the control circuit consisted synchronous closing circuit, over- current detecting circuit and sensing circuit of rate of rise of fault current.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.9
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• pp.391-396
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• 2005

In this paper the modeling of interrupting characteristics of a high voltage current limiting fuse to be used in a power distribution system is introduced. In order to reduce the level of energy which can be absorbed by equipment during fault current flow, a high voltage current limiting fuse can generate a high voltage at the fuse terminals. Consequently it is necessary to model and analyze precisely the voltage and current variation during a CL fuse action. The characteristics of CL fuse operation modeled by electrical components have been performed with less than 6 [$\%$] errors. So the fuse designer or manufacturer can estimate the characteristics of CL fuse operation by using this modeling. The Electro Magnetic Transient Program (EMTP) is used to develop the modeling.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• Journal of Power Electronics
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• v.19 no.4
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• pp.989-999
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• 2019

This paper proposes a fault-tolerant control strategy with finite control set model predictive control (FCS-MPC) based on hierarchical optimization for five-level H-bridge neutral-point-clamped (5L-HNPC) inverter-fed induction motor drives. Fault-tolerant operation is analyzed, and the fault-tolerant control algorithm is improved. Adopting FCS-MPC based on hierarchical optimization, where the voltage is used as the controlled objective, called model predictive voltage control (MPVC), the postfault controller is simplified as a two layer control. The first layer is the voltage jump limit, and the second layer is the voltage following control, which adopts the optimal control strategy to ensure the current following performance and uniqueness of the optimal solution. Finally, simulation and experimental results verify that 5L-HNPC inverter-fed induction motor drives have strong fault tolerant capability and that the FCS-MPVC based on hierarchical optimization is feasible.

• Progress in Superconductivity and Cryogenics
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• v.4 no.1
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• pp.99-104
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• 2002

This study deals with the optimal design of a DC reactor type high-Tc superconducting fault current limiter(SFCL). The condition in which the cost function is minimized under given constraints is one of the things to be first considered in developing SFCLS. This condition is a group of the values corresponding to the variables the cost function depends on. In this paper, the length of tape was taken as a dependent variable, the inductance of DC reactor and the turns ratio of magnetic core reactors as independent variables. For the SFCL available at the level of 6.6kV-200A, we examined 4 cases; at the fault times of 80msec, 50msec, 30msec and 10msec. Since thyristors would be utilized instead of diodes, we chose the result at 10msec as the basic data. Considering safety factor 30%, our optimal design was decided to be the inductance 570mH, the critical current over 620A, the turns ratio 0.89 and the fault time within 20msec.

• Transactions on Electrical and Electronic Materials
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• v.8 no.5
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• pp.222-225
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• 2007

In this paper, we compared the current limiting characteristics of both the hybrid type and the flux-lock type superconducting fault current limiters(SFCLs), which have a magnetic coupling structure between a primary winding and several secondary windings. The limiting impedances of two SFCLs were derived from each equivalent circuit considering the design parameters of SFCL such as the self-inductance of secondary winding and the resistance of $high-T_C$ superconducting(HTSC) element. Through the comparison for the limiting impedances of two SFCLs considering the dependence of the HTSC element's resistance on the applying voltage into the SFCL, the hybrid type SFCL was confirmed to have larger limiting impedance with smaller resistance of HTSC element than the flux-lock type SFCL. It was expected from the analysis that the hybrid type SFCL was more advantageous than the flux-lock type SFCL from the viewpoint of the fault current limiting level.