• Journal of Positioning, Navigation, and Timing
• /
• 제4권4호
• /
• pp.161-171
• /
• 2015

Alternative binary offset carrier (AltBOC) signals can be approximated by four synchronized direct sequence spread spectrum (DSSS) signals, each pair of which is a quadrature phase shift keyed (QPSK) signal at a different frequency. Therefore, depending on the strength of an incoming AltBOC signal, an acquisition technique can reduce the mean acquisition time (MAT) by searching the four DSSS signals asynchronously; the search for each of the four DSSS signals can start at one of the evenly separated hypotheses on the two-dimensional hypothesis space. And detection sensitivity can be improved by multiple levels when different numbers of search results for the same hypothesis are combined. In this paper, we propose a fast AltBOC acquisition technique that has an asynchronous search strategy and efficiently utilizes the output of the four search results to increase the sensitivity level when sensitivity improvement is needed. We provide a complete theoretical analysis and demonstrate with numerous Monte Carlo simulations that the MAT of the proposed technique is much smaller than conventional AltBOC acquisition techniques.

• 대한전기학회논문지:시스템및제어부문D
• /
• 제50권10호
• /
• pp.479-485
• /
• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.1201-1204
• /
• 2003

This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35${\mu}{\textrm}{m}$ CMOS process.

• 한국정보처리학회:학술대회논문집
• /
• 한국정보처리학회 2009년도 춘계학술발표대회
• /
• pp.1352-1355
• /
• 2009

TCP에서 사용되는 혼잡제어(Congestion control)는 많은 이점이 있지만 그에 상응하는 단점이 존재한다. 가장 널리 사용되고 있는 TCP-Reno는 혼잡이 발생되면 혼잡 윈도우(Congestion Window)크기를 절반으로 줄이고 빠른 회복(fast recovery), 빠른 재전송(fast transmit)을 수행한다. 하지만 네트워크가 고속 네트워크로 접어들면서 효율적인 측면에서 이러한 기법들을 적용하기에는 문제가 따른다. 현재 사용되고 있는 TCP는 혼잡이 발생하면 선형적으로 점진적으로 증가 하기 때문에 많은 대역폭을 지원하는 고속 네트워크에서는 이러한 TCP의 혼잡 제어가 오히려 비 효율적이다. 본 논문에서는 이러한 문제점을 해결하기 위해 혼잡 윈도우 증가율을 추가한 혼잡제어 기법인 TCP-FBA(Fast Bandwidth Acquisition)를 제안한다.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제12권11호
• /
• pp.5481-5495
• /
• 2018

Single pixel imaging technology has developed for years, however the video acquisition on the single pixel camera is not a well-studied problem in computer vision. This work proposes a new scheme for single pixel camera to acquire video data and a new regularization for robust signal recovery algorithm. The method establishes a single pixel video compressive sensing scheme to reconstruct the video clips in spatial domain by recovering the difference of the consecutive frames. Different from traditional data acquisition method works in transform domain, the proposed scheme reconstructs the video frames directly in spatial domain. At the same time, a new regularization called spatial cluster is introduced to improve the performance of signal reconstruction. The regularization derives from the observation that the nonzero coefficients often tend to be clustered in the difference of the consecutive video frames. We implement an experiment platform to illustrate the effectiveness of the proposed algorithm. Numerous experiments show the well performance of video acquisition and frame reconstruction on single pixel camera.

• 한국통신학회논문지
• /
• 제33권6A호
• /
• pp.685-692
• /
• 2008

본 논문에서는 Inmarsat (International Marine Satellite) mini-m 시스템의 하향 링크 수신기를 위한 timing recovery 루프를 제안한다. Inmarsat mini-m 시스템 규격에서 요구하는 frequency tolerance는 ${\pm}924$ Hz (signal bandwidth: 2.4 kHz) 이며, timing acquisition 시간은 하나의 UW (Unique Word) 신호 구간인 15ms 이기 때문에 주파수 옵셋에 강인하고 UW 신호 구간에서의 빠른 aquisition 이 가능한 루프 설계가 요구된다. 이에 따라 본 논문에서는 주파수 옵셋에 강인하고 빠른 aquisition 이 가능한 timing recovery 루프를 제안하였으며, 제안된 timing recovery 루프는 UW detector와 UW detector에 의해 검출된 UW 신호를 이용한 timing recovery 루프를 연동한 구조이다. UW detector는 주파수 옵셋 환경에서 안정적인 성능을 위해 차동 기반의 noncoherent detector 방식을 적용하였으며, TED (Timing Error Detector) 알고리즘은 기존의 GAD (Gardner Detector) 알고리즘 대신 본 논문에서 제안하는 UW 신호를 이용한 차동 기반의 ELD (Early Late Detector) 알고리즘 적용하였다. 제안된 방식과 기존의 GAD와의 성능 비교를 통해 제안된 방식이 만족스러운 성능과 신뢰성 있는 동작이 가능함을 입증하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 하계학술대회 논문집
• /
• pp.271-274
• /
• 2001

In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$ ∼ $\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.

• 한국항해항만학회:학술대회논문집
• /
• 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.2
• /
• pp.395-398
• /
• 2006

In this paper, for implementing a real-time software GNSS receiver we propose the highly efficient and fast algorithms such as partial down-conversion, phase rotator, composite I&Q accumulation, Virtual DCO technique, and parallel acquisition using FFT. When the proposed algorithms are used, more 30 tracking channels with 3 tracking arm(early-prompt-late) is operated real-time on Intel 2.8GHz personal computer. Also, the partial down-conversion reduces the FFT size, for parallel acquisition, to 1/8 of conventional FFT-size and the program size includes map is not exceed 1Mbyte. Finally, the proposed real-time software GNSS receiver using the proposed algorithms provides the navigation solution with below 10 meter rms error.

• 한국통신학회논문지
• /
• 제35권4C호
• /
• pp.371-376
• /
• 2010

본 논문에서는 고차의 QAM 시스템을 위한 새로운 고속 반송파 복원 알고리즘을 제안한다. 제안된 방식은 수신 심볼 간 위상차를 이용하여 반송파 주파수 오프셋을 직접 검출하며, 이를 기존의 반송파 복원 방식에 적용함으로써 넓은 주파수 추적 범위와 빠른 수렴 속도를 제공하는 반송파 복원을 수행할 수 있다. 시뮬레이션을 통하여 제안된 반송파 복원 방식이 주파수 오프셋이 크고 신호 대 잡음비가 낮은 상황에서도 짧은 수렴 시간을 가지는 것을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
• /
• pp.1188-1191
• /
• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.