• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.3
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• pp.83-90
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• 2001

This paper resents an algorithm for the optimal parameter selection of a power system stabilizer in a single machine-infinite bus system through the external equivalent transmission line. This method is one of the classical techniques by changing the PSS gain to allocate properly pole-zero positions. All the PSS parameters are obtained by solving a set of algebraic equations for the system constants depend on a variety of machine loadings and system external impedances, the natural oscillation modes, and the damping characteristics. And this algorithm was written in a simple software program using MATLAB.

• Proceedings of the Korea Society for Simulation Conference
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• 1992.10a
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• pp.5-5
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• 1992

The DEVS(discrete event system specification) formalism describes a discrete event system in a hierarchical, modular form. DEVSIM++ is C++ based general purpose DEVS abstract simulator which can simulate systems to be modeled by the DEVS formalism in a sequential environment. We implement P-DEVSIM++ which is a parallel version of DEVSIM++. In P-DEVSIM++, the external and internal event of models can be processed in parallel. To process in parallel, we introduce a hierarchical distributed simulation technique and some optimistic distributed simulation techniques. But in our algorithm, the rollback of a model is localized itself in contrast to the Time Warp approach. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• Journal of the Korea Society for Simulation
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• v.1 no.1
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• pp.64-76
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• 1992

The DEVS(discrete event system specificaition) formalism specifies a discrete event system in a hierarchical, modular form. DEVSIM++ is a C++based general purpose DEVS abstract simulator which can simulate systems modeled by the DEVS formalism in a sequential environment. This paper describes P-DEVSIM++which is a parallel version of DEVSIM++ . In P-DEVSIM++, the external and internal event of DEVS models can by processed in parallel. For such processing, we propose a parallel, distributed optimistic simulation algorithm based on the Time Warp approach. However, the proposed algorithm localizes the rollback of a model within itself, not possible in the standard Time Warp approach. An advantage of such localization is that the simulation time may be reduced. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• Transactions of the Korean hydrogen and new energy society
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• v.34 no.3
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• pp.246-255
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• 2023

Due to lack of hydrogen charging stations and hydrogen supply compared to the supply of hydrogen vehicles, social phenomena such as 2-hour queues and restrictions on charging capacity are occurring, which negatively affects the spread of hydrogen vehicles. In order to resolve these problems, it is essential to have a strategic operation of the hydrogen charging stations. To establish operational strategies, it is necessary to derive customer demand patterns and characteristics through the analysis of sales data. This study derived the demand patterns and characteristics of customers visiting hydrogen charging stations through data analysis from various perspectives, such as charging volume, charging speed, number of visits, and correlation with external factors, based on the hydrogen sales data of off-site hydrogen charging stations located in domestic residential areas.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1129-1138
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• 2019

Since substations are structurally complex due to the concentration of protection coordination facilities with substation facilities for long distance power transmission, it is difficult to design a protection coordination system to minimize the spreading effect of the fault when a fault occurs on transmission line or distribution line. Therefore, in this paper, the bus configuration and the basic logic of protection coordination that have a major influence on the reliability of substation power supply were analyzed, and the substation protection coordination logic to detect internal and external faults was developed based on EMTP-RV. As the basic logic of substation protection coordination, the percent differential protection relay logic for substation internal fault detection and the overload protection relay logic for inference of external failure were modeled. Finally, the 154kV substation including the protection coordination logic was modeled using EMTP-RV, and the effectiveness of the protection coordination design methodology was confirmed through the several fault simulation cases based on EMTP-RV.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.57-62
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• 2011

In this paper, an efficient architecture for MFVLD(Multi-Format Variable Length Decoder) which can process H.264, MPEG-2, MPEG-4, AVS, VC-1 bitstream is proposed. The proposed MF-VLD is designed to be adapted to the MPSOC (Multi-processor System on Chip) architecture, uses bit-plane algorithm for the processing of inverse quantized data to reduce the width of AHB bus. External SDRAM is used to minimize the internal memory size. In this architecture, the adding or removing each variable length decoder can be easily done by using multiplexor. The designed MF-VLD can be operated in 200MHz at 0.18um process. The gate size is 657K gate and internal memory size is 27Kbyte.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.197-199
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• 2018

Recently, many industrial instruments face the problem of protocol compatibility with the external monitoring and control system. This paper is prepared in the main control board to support the industrial communication protocol conversion, control, and monitoring. The industrial communication gateway module is also designed to ensure that the protocol conversion of CAN bus and Ethernet. The main board processor is used the Atmega2560, and placed 4ea RS485 serial slots for sub-board. One of them is used for communication CAN bus and Ethernet. It provides analog and digital I / O through each of the slots is used for control and monitoring.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.155-157
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• 2001

This paper presents an comparative study on the effect of SSSC and UPFC to the power system static analysis. SSSC is used to control active power flow in transmission lines by controlling the phase angle of the injected voltage source which is in rectangular to the line current. UPFC is used to control the magnitude and phase of the injected voltage sources which are connected both in series and in parallel with the transmission line to control power flow and bus voltage. To compare the effect of SSSC and UPFC in power system static analysis, the PSS/E simulation program is used. As the FACTS device model such as SSSC and UPFC is not provided in PSS/E yet, an equivalent load model is used. This procedure is implemented by IPLAN which is an external macro program of PSS/E. The simulation results show that UPFC is more effective to improve bus voltage than SSSC in power system static analysis.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.281-283
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• 2016

Recently, many industrial instruments face the problem of protocol compatibility with the external monitoring and control system. This paper is prepared in the main control board to support the industrial communication protocol conversion, control, and monitoring. The industrial communication gateway module is also designed to ensure that the protocol conversion of CAN bus and Ethernet. The main board processor is used the Atmega2560, and placed 4ea RS485 serial slots for sub-board. One of them is used for communication CAN bus and Ethernet. It provides analog and digital I / O through each of the slots is used for control and monitoring.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.515-520
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• 1998

In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.