• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5375-5400
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• 2016

IOMMU is a hardware unit that is indispensable for DMA. Besides address translation and remapping, it also provides I/O virtual address space isolation among devices and memory access control on DMA transactions. However, currently commodity virtualization platforms lack of IOMMU virtualization, so that the virtual machines are vulnerable to DMA security threats. Previous works focus only on DMA security problem of directly assigned devices. Moreover, these solutions either introduce significant overhead or require modifications on the guest OS to optimize performance, and none can achieve high I/O efficiency and good compatibility with the guest OS simultaneously, which are both necessary for production environments. However, for simulated virtual devices the DMA security problem also exists, and previous works cannot solve this problem. The reason behind that is IOMMU circuits on the host do not work for this kind of devices as DMA operations of which are simulated by memory copy of CPU. Motivated by the above observations, we propose an IOMMU para-virtualization solution called PVIOMMU, which provides general functionalities especially DMA security guarantees for both directly assigned devices and simulated devices. The prototype of PVIOMMU is implemented in Qemu/KVM based on the virtio framework and can be dynamically loaded into guest kernel as a module, As a result, modifying and rebuilding guest kernel are not required. In addition, the device model of Qemu is revised to implement DMA access control by separating the device simulator from the address space of the guest virtual machine. Experimental evaluations on three kinds of network devices including Intel I210 (1Gbps), simulated E1000 (1Gbps) and IB ConnectX-3 (40Gbps) show that, PVIOMMU introduces little overhead on DMA transactions, and in general the network I/O performance is close to that in the native KVM implementation without IOMMU virtualization.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.2
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• pp.74-81
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• 2002

In general, a multipath generator consists of a time delay generator, phase rotator, and amplitude attenuator, and is implemented mostly in an analog manner. Analog, or partially analog versions of a multipath generator is disadvantageous in that they may suffer from problems associated with component aging and adjustment, signal fidelity degradation stemming from repeated A/D and D/A conversion use of high frequency to achieve fine i.e., subsample fractional tin delays. This paper presents the design and implementation methodology of a full digital multipath generator which can be used in performance evaluations of digital terrestrial television as well as communications, receivers. In particular, an efficient practical method is proposed which can achieve both integer and fractional time delays simultaneously, without placing restrictions on the allowable system master clock frequency. The proposed algorithm lends itself to minimizing hardware implementation cost by relegating some fixed put of the computation involved to an IBM PC. The proposed multipath generator occupies only a single digital board space, and its experimental results are provided to corroborate the proposed implementation methodology.

• KIISE Transactions on Computing Practices
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• v.21 no.3
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• pp.173-182
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• 2015

Motion control systems are widely deployed in various industrial automation processes. The motion controller, which is a key element of motion control systems, has stringent real-time constraints. The controller must provide a short and deterministic control message transmission cycle, and minimize the actuation deviation among motor drives. To meet these requirements, hardware-based proprietary controllers have been prevalent. However, since it is becoming difficult for such an approach to meet increasing needs of system interoperability and scalability, nowadays, software-based universal motion controllers are regarded as their substitutes. Recently, embedded motion controller solutions are gaining attention due to low cost and relatively high performance. In this paper, we designed and implemented an embedded motion controller on an ARM-based evaluation board by using Xenomai real-time kernel and other open source software components. We also measured and analyzed the performance of our embedded controller under a realistic test-bed environment. The experimental results show that our embedded motion controller can provide relatively deterministic performance with synchronized control of three motor axis at 2 ms control cycle.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2035-2044
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• 2016

In order to match the voltages between high voltage battery stacks and low voltage super-capacitors with a high conversion efficiency in hybrid energy sources electric vehicles (HESEVs), a high ratio bidirectional DC-DC converter with a synchronous rectification H-Bridge is proposed in this paper. The principles of high ratio step-down and step-up operations are analyzed. In terms of the bidirectional characteristic of the H-Bridge, the bidirectional synchronous rectification (SR) operation is presented without any extra hardware. Then the SR power switches can achieve zero voltage switching (ZVS) turn-on and turn-off during dead time, and the power conversion efficiency is improved compared to that of the diode rectification (DR) operation, as well as the utilization of power switches. Experimental results show that the proposed converter can operate bidirectionally in the wide ratio range of 3~10, when the low voltage continuously varies between 15V and 50V. The maximum efficiencies are 94.1% in the Buck mode, and 93.6% in the Boost mode. In addition, the corresponding largest efficiency variations between SR and DR operations are 4.8% and 3.4%. This converter is suitable for use as a power interface between the battery stacks and super-capacitors in HESEVs.

• The Journal of the Korea Contents Association
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• v.8 no.9
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• pp.42-54
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• 2008

In recent years, embedded systems have been expanding their application domains from traditional embedded systems such as military weapons, robots, satellites and digital convergence systems such as celluar phones, PMP(Portable Multimedia Player), PDAs(Personal Digital Assistants) to Next Generation Personal Computers(NGPCs) such as eating PCs, wearable computers. The NGPCs are network-based, human-centric digital information devices diverged from the traditional PCs used mainly for document writing, internet searching and database management. Wearable computers with battery capacity and memory size limitations have to use real-time operating systems with small footprints and low power management techniques to provide user's QoS in spite of hardware constraints. In this paper, we have designed and implemented a low-power RTOS (called eRTOS) for wearable computers. The implemented eRTOS has 18KB footprints and the dynamic power management and the device power management schemes are adapted in it. Experimental results with wearable computer applications show that the low power techniques could save energy up to 47 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.4
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• pp.267-272
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• 2016

Wireless sensor networks (WSNs) are vulnerable to external intrusions due to the wireless communication characteristics and limited hardware resources. Thus, the attacker can cause sinkhole attack while intruding the network. INSENS is proposed for preventing the sinkhole attack. INSENS uses the three symmetric keys in order to prevent such sinkhole attacks. However, the sinkhole attack occurs again, even in the presence of INSENS, through the compromised node because INSENS does not consider the node being compromised. In this paper, we propose a method to counter the sinkhole attack by considering the compromised node, based on the neighboring nodes' information. The goals of the proposed method are i) network reliability improvement and ii) energy conservation through effective prevention of the sinkhole attack by detecting compromised nodes. The experimental results demonstrate that the proposed method can save up to, on average, 19.90% of energy while increasing up to, on average, 71.50%, the report reliability against internal sinkhole attacks in comparison to INSENS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.567-575
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• 2011

The two most popular virtual machine allocation schemes, both match making and round robin, do consider hardware specifications such as CPU, RAM, and HDD, but not CPU usage, which results in balanced resource distribution, but not in balanced resource usage. Thus, in this paper a new virtual machine allocation scheme considering current CPU usage rate is proposed while retaining even distribution of node resources. In order to evaluate the performance of the proposed scheme, a cloud computing platform composed of three cloud nodes and one front end is implemented. The proposed allocation scheme was compared with both match making and round robin schemes. Experimental results show that the proposed scheme performs better in even distribution of overall CPU usage, which results in efficient load balancing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.325-327
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• 2015

Startup in the aging society is much harder than finding employment. However, we did an experimental research that the elderly are able to develop in the field of IoT via this education. Through this IT startup education, those people who can do develop and implement and they are able to start new business by develop new item. Installing education between hardware and software about Arduino and Scratch's methods have great effect on IT startup education for the elderly before solving problem which have existing programming education. While the IT startup education through IoT is more difficult subject compared to general education subject, this paper shows an easily accessible research outcome for the elderly through startup education. This paper proved that practical uses through the results.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.569-576
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• 2011

This paper proposes a new dead time compensation method for a PWM inverter. Recently, PWM inverters are extensively used for industry applications, such as ac motor drives, distributed grid-connected systems and a static synchronous compensator (STATCOM). Nonlinear characteristics of the switch and the inverter dead time cause a current distortion and deterioration of power quality. The dominant harmonics in the output current are the $5^{th}$ and $7^{th}$ harmonics in the stationary frame, and the $6^{th}$ harmonics in the synchronous rotating frame. In this paper, a resonant controller which compensates the $6^{th}$ harmonics in the synchronous rotating frame is proposed. This method does not require any off-line experimental measurements, additional hardware and complicated mathematical computations. Furthermore, the proposed method is easy to implement and does not cause any stability problem.