• The Research Journal of the Costume Culture
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• v.25 no.1
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• pp.48-63
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• 2017

When digital media and images are combined, their significant sociocultural impacts can be exercised. Therefore, this study analyzes digital images shown in such trends of digital media compared to the digital fashion from an aesthetic perspective. Research and empirical studies are focused upon to analyze the aesthetic characteristics of digital fashion. Digital Fashion comprehensively refers to fashion design using computers and software, and is considered as "Fashion Design utilizing Digital Technologies" including computer software and hardware perspectives, so that it may be renamed "Digital Fashion." The esthetic characteristics shown in the Digital Fashion defined above are analyzed according to how media philosophers conceptualize the digital image. First, from the perspective of creation, Digital Fashion Images are technical images produced by computers. Uncanny characteristics expressed through virtual images look more realistic than the actual ones used in experimental works of fashion designers. Such virtuality dynamically expresses various colors and fabric patterns through lights using digital technologies that do not yet exist in cloth form, rather in a non-material form of dynamic virtual imagery. Digital fashion images on monitors express digital fashion designs by shaping virtual images through 3D printing. Second, Digital Fashion Images from the perspective of acceptance are created through deconstruction, while fashion has only been previous viewed visually, Digital Fashion delivers immersions of visual touches as if directly experienced for accepters. Digital Fashion will continuously develop and become more influential as it converges with digital media.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.114-124
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• 2014

HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth.

• Journal of Korea Game Society
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• v.5 no.3
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• pp.39-47
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• 2005

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simulaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that proposed architecture achieves almost linear speedup at best case even in sixteen rasterizer

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.6
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• pp.496-503
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• 2009

In this paper, a new three-phase interleaved isolated high efficiency boost dc-dc converter with active clamp is proposed. The converter is capable of increased power transfer due to its three-phase power configuration, and it reduces the rms current per phase, thus reducing conduction losses. Further, interleaved operation of three-phase boost converter reduces overall ripple current, which is imposed into fuel cells and realizes smaller sized filter components, increasing effective operating frequency and leading to higher power density. Each output current of three-phase boost converter is combined by the three-phase transformer and flows in the continuous conduction mode by the proposed three-phase PWM strategy. An efficiency of above 96% is mainly achieved by reducing conduction losses and switching losses are reduced by the action of active clamp branches, as well. The proposed converter and three-phase PWM strategy are analyzed, simulated and implemented in hardware. Experimental results are obtained on a 500 W prototype unit, with all of the design verified and analyzed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1605-1614
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• 2009

The technique of simultaneous localization and mapping is the most important research topic in mobile robotics. In the process of building a map in its available memory, the robot memorizes environmental information on the plane of grid or topology. Several approaches about this technique have been presented so far, but most of them use mapping technique as either grid-based map or topology-based map. In this paper we propose a frame of solving the SLAM problem of linking map covering, map building, localizing, path finding and obstacle avoiding in an automatic way. Some algorithms integrating grid and topology map are considered and this make the SLAM performance faster and more stable. The proposed scheme uses an occupancy grid map in representing the environment and then formulate topological information in path finding by A${\ast}$ algorithm. The mapping process is shown and the shortest path is decided on grid based map. Then topological information such as direction, distance is calculated on simulator program then transmitted to robot hardware devices. The localization process and the dynamic obstacle avoidance can be accomplished by topological information on grid map. While mapping and moving, pose of the robot is adjusted for correct localization by implementing additional pixel based image layer and tracking some features. A laser range finer and electronic compass systems are implemented on the mobile robot and DC geared motor wheels are individually controlled by the adaptive PD control method. Simulations and experimental results show its performance and efficiency of the proposed scheme are increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.1
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• pp.43-50
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• 2003

Today, the demand of image acquisition systems grows as the multimedia applications go on increasing greatly. Among the systems, film scanner is one of the systems, which can acquire high quality and high resolution images. However due to the nonlinear characteristic of the light source and sensor, colors of the original film image do not correspond to the colors of the scanned image. Therefore color correction mr the scanned digital image is essential in the film scanner. In this paper, polynomial regression method is applied for the color correction to CIE $L^{*}$ $a^{*}$ $b^{*}$ color model data converted from RGB color model data. A1so a film scanner hardware with 12 bit color resolution for each R, G, B and 2400 dpi was implemented by using TMS320C32 DSP chip and high resolution line sensor. An experimental result shows that the average color difference ($\Delta$ $E^{*}$$_{ab}$ ) is reduced from13.48 to 8.46.6.6.6.6.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.69-76
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• 2006

This paper proposes a self-repair system which is able to self-repair in cell unit by imitating the structure of living beings. Because the data of artificial cells move even diagonally, our system can self-repair faults not in column unit, but in cell unit. It leads to design an efficient self-repair system for multiple faults. Moreover, in artificial cell design, the usage of logic-based design method has smaller system size than that of the previous register-based design method. Our experimental result for 2-bit up/down counter shows 40.3% reduction in hardware overhead, compared to the previous method [6].

• Progress in Medical Physics
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• v.3 no.1
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• pp.71-78
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• 1992

This study describes the design of the biophysiological signal processing analyzer which can collect and analyze the biosignal raw data. System hardware is consisted of the IBM PC AT. pre-amplifier. AID converter, Counter/Timer. and RS-232C processor. Biophysiological signal data were processed by the software digital filter. FFT and graphic processing routine. The tachogram and FFT of the the peak to peak interval time was accomplished by the Graphic user interface software using the biophysiological signal processed data. Using this system. the powerspectrum of the heart rate variability during the long term could be observed. Experimental results of this system approach our purpose. which is improved the cost performance. easy to use. reducing raw-data noise and optimizing model for digital filter.

• Journal of IKEEE
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• v.19 no.3
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• pp.400-406
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• 2015

In this paper, we designed a decision feedback based diversity modem hardware architecture for IEEE802.11p WAVE and tested the modem on the road with car attached shark antenna. One of the dual channel modem and the diversity single modem with maximum ratio combining algorithm can be selected on the designed architecture. The designed modem have been implemented on the Xillinx Kintex7 FPGA. We tested the modem performance on the smart highway experience road. As experimental results, we can verify the performance of the diversity modem on real road and the enlarged communication range by more than 100%.