• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.209-210
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability.

• Journal of information and communication convergence engineering
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• 제20권3호
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• pp.212-218
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• 2022

The performance of vision-based intelligent systems, such as self-driving cars and unmanned aerial vehicles, is subject to weather conditions, notably the frequently encountered haze or fog. As a result, studies on haze removal have garnered increasing interest from academia and industry. This paper hereby presents a 4K-capable hardware implementation of an efficient haze removal algorithm with the following two improvements. First, the depth-dependent haze distribution is predicted using a linear model of four haze-relevant features, where the model parameters are obtained through maximum likelihood estimates. Second, the approximated quad-decomposition method is adopted to estimate the atmospheric light. Extensive experimental results then follow to verify the efficacy of the proposed algorithm against well-known benchmark methods. For real-time processing, this paper also presents a pipelined architecture comprised of customized macros, such as split multipliers, parallel dividers, and serial dividers. The implementation results demonstrated that the proposed hardware design can handle DCI 4K videos at 30.8 frames per second.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권4호
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• pp.1146-1165
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• 2022

A huge amount of data in the form of videos and images is being produced owning to advancements in sensor technology. Use of low performance commodity hardware coupled with resource heavy image processing and analyzing approaches to infer and extract actionable insights from this data poses a bottleneck for timely decision making. Current approach of GPU assisted and cloud-based architecture video analysis techniques give significant performance gain, but its usage is constrained by financial considerations and extremely complex architecture level details. In this paper we propose a data pipeline system that uses open-source tools such as Apache Spark, Kafka and OpenCV running over commodity hardware for video stream processing and image processing in a distributed environment. Experimental results show that our proposed approach eliminates the need of GPU based hardware and cloud computing infrastructure to achieve efficient video steam processing for face detection with increased throughput, scalability and better performance.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제4권6호
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• pp.1294-1310
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• 2010

User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제6권4호
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• pp.448-456
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• 2000

설계되는 시스템의 규모가 커지고 복잡해지므로 이를 빠른 시간 내에 효율적으로 검증하기 위한 상위 단계에서의 검증 기술의 개발이 중요하게 되었다. 본 연구에서는 하드웨어와 소프트웨어가 혼합되어 있는 시스템을 위한 상위 단계에서의 검증기술을 개발하였다. 에뮬레이션 또는 시뮬레이션만을 수행하는 것보다 빠르고 우수하게 기능적으로 검증하기 위해, 하드웨어와 소프트웨어 부분으로 분할한 후 인터페이스 회로를 이용하여 구현 가능하도록 하였다. 그리고, 상위 단계의 회로를 쉽게 하드웨어를 이용하여 검증하기 위한 설계 지침들을 제시하였다. 본 방법을 이용하여 리드-솔로몬 디코더 회로에 대한 검증을 수행한 결과 시뮬레이션만을 수행한 경우에 비하여 modified Euclid 알고리즘 수행 블록은 12,000배 이상의 속도로 검증을 수행할 수 있었으며, 전체 검증 시간도 반 이하로 줄었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1047_1048
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• 2009

This paper describes comparative analysis results about the dynamic interaction of interconnected wind power system using the actual-size hardware simulator and the simulation model with PSCAD/EMTDC. The hardware simulator, which is composed of 2.0MVA induction motor with drive system and 1.5MW doubly-fed induction generator, was built and tested in Go-Chang Test Site of KEPCO for analyzing the dynamic interaction with the interconnected distribution system. The operation of hardware simulator was verified through comparative analysis between experimental results and simulation results obtained by simulation model with PSCAD/EMTDC. The developed hardware simulator and simulation model could be effectively used for analyzing the dynamic interaction, which has various phenomena depending on the wind variation and the network state of interconnected power system.

• 전기학회논문지P
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• 제58권3호
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• pp.263-269
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• 2009

This paper describes comparative analysis results about the dynamic interaction of interconnected wind power system using the actual-size hardware simulator and the simulation model with PSCAD/EMTDC. The hardware simulator, which is composed of 2.0MVA induction motor with drive system and 1.5MW doubly-fed induction generator, was built and tested in Go-Chang Test Site of KEPCO for analyzing the dynamic interaction with the interconnected distribution system. The operation of hardware simulator was verified through comparative analysis between experimental results and simulation results obtained by simulation model with PSCAD/EMTDC. The developed hardware simulator and simulation model could be effectively used for analyzing the dynamic interaction, which has various phenomena depending on the wind variation and the network state of interconnected power system.

• 전기학회논문지
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• 제63권8호
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• pp.1046-1054
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• Nuclear Engineering and Technology
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• 제52권7호
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• pp.1462-1470
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• 2020

Reliability in safety-critical systems and equipment is of vital importance, so the probabilistic safety assessment (PSA) has been widely used for many years in the nuclear industry to address reliability in a quantitative manner. As many nuclear power plants (NPPs) become digitalized, evaluating the reliability of safety-critical software has become an emerging issue. Due to a lack of available methods, in many conventional PSA models only hardware reliability is addressed with the assumption that software reliability is perfect or very high compared to hardware reliability. This study focused on developing a new method of safety-critical software reliability quantification, derived from hardware-software integrated environment testing. Since the complexity of hardware and software interaction makes the possible number of test cases for exhaustive testing well beyond a practically achievable range, an importance-oriented testing method that assures the most efficient test coverage was developed. Application to the test of an actual NPP reactor protection system demonstrated the applicability of the developed method and provided insight into complex software-based system reliability.

• 한국정보과학회논문지:정보통신
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• 제29권6호
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• pp.625-634
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• 2002

암호화는 송수신자 사이에 메시지 전달이 비밀스럽게 이루어 질 수 있도록 보장해주는 기법이다. 이러한 암호화 알고리즘은 높은 계산량을 필요로 하며, 결과적으로 프로세서 자원을 과도하게 사용하는 문제를 가지고 있다. 이러한 문제점을 해결하기 위하여 암호화 알고리즘을 하드웨어 방식으로 구현함으로써 시스템의 부하를 줄여주는 기법이 제시되고 있다. 본 논문에서는 하드웨어 암호화 기법에 대한 설계 및 구현에 대해서 언급하고 있으며, 하드웨어 암호화 알고리즘과 소프트웨어 암호화 알고리즘에 대한 성능을 비교 분석하였다. 실험 결과에서, 계산 복잡도가 낮은 DES 알고리즘은 하드웨어 방식을 적용하여도 높은 입출력 오버헤드에 의해서 성능이 향상되지 않지만, 계산 복잡도가 높은 Triple DES는 하드웨어 방식을 적용하였을 때, 대략 2-4배 성능이 향상됨을 볼 수 있었다.