Browse > Article

Design and Performance Evaluation of Hardware Cryptography Method  

Ah, Jae-Yong (고려대학교 컴퓨터학과)
Ko, Young-Woong (고려대학교 컴퓨터학과)
Hong, Cheol-Ho (고려대학교 컴퓨터학과)
Yoo, Hyuck (고려대학교 컴퓨터학과)
Abstract
Cryptography is the methods of making and using secret writing that is necessary to keep messages private between two parties. Cryptography is compute-intensive algorithm and needs cpu resource excessively. To solve these problems, there exists hardware approach that implements cryptographic algorithm with hardware chip. In this paper, we presents the design and implementation of cryptographic hardware and compares its performance with software cryptographic algorithms. The experimental result shows that the hardware approach causes high I/O overheads when it transmits data between cryptographic board and host cpu. Hence, low complexity cryptographic algorithms such as DES does not improve the performance. But high complexity cryptographic algorithms such as Triple DES improve the performance with a high rate, roughly from two times to Sour times.
Keywords
DES; Triple DES; cryptographic algorithm;
Citations & Related Records
연도 인용수 순위
  • Reference
1 김 철, 암호학의 이해, 영풍문고, 1996
2 H. Feistel, 'Cryptography and Computer Privacy,' Scientific American. Vol 228, 1973
3 National Institute of Standards and Technology, 'Data Encryption Standard,' FIPS Publication 46-1, January 1988
4 J. Dyer, R. Perez, S.W. Smith, and M. Lindemann, 'Application support architecture for a high-performance, programmable secure coprocessor,' 22nd National Information Systems Security Conference, October 1999
5 Tygar, J.D. and Yee, B.S., 'Secure Coprocessors in Electronic Commerce Applications,' Proceedings 1995 USENIX Electronic Commerce Workshop, 1995, New York
6 P. C. Clark and L. J. Hoffmann. 'BITS: A Smartcard Protected Operating System,' Communications of the ACM. 37: 66-70. November 1994   DOI   ScienceOn
7 S.W. Smith, S.H. Weingart. 'Building a High-Performance, Programmable Secure Coprocessor,' Computer Networks (Special Issue on Computer Network Security.) 31: 831-860. April 1999   DOI   ScienceOn
8 S. W. Smith. 'Secure Coprocessing Applications and Research Issues,' Los Alamos Unclassified Release LAUR-96-2805, Los Alamos National Laboratory. August 1996
9 S. W. Smith and V. Austel. 'Trusting trusted hardware: Towards a formal model for programmable secure coprocessors,' In Proceedings of the Thrid USENIX Workshop on Electronic Commerce, September 1998
10 Writing Device Drivers, Sun Microsystems Inc. 1998
11 J. D. Tygar and Bennet Yee. 'Dyad: A system for using physically secure coprocessors,' Technical report, Carnegie Mellon University, May 1991
12 128비트 블록 암호알고리즘(SEED) 개발 및 분석보고서, 정보보호진흥원 연구보고서 1998.12
13 A. Elbirt, 'An FPGA Implementation and Performance Evaluation of the CAST-256 Block Cipher,' Technical Report, Cryptography and Information Security Group, Electrical and Computer Engineering Department, Worcester Polytechnic Institute, Worcester, MA, May 1999
14 Tom Shanley, Don Anderson, PCI System Architecture, MindShare Inc.
15 S.W.Smith,E.R.Palmer,S.HWeingart.'Using a High-Performance, Programmable Secure Coprocessor,' Proceedings, Second International Conference on Financial Cryptography. Springer-Verlag LNCS, 1998   DOI   ScienceOn
16 C . K. Koc, 'RSA Hardware Implementation,' TR 801, RSA Laboratories, April 1996
17 http://www.stitec.com/product/scc1021.html
18 Kaps, J., and Paar, C., 'Fast DES Implementation for FPGAs and its Application to a Universal Key-Search Machine,' 5th Annual Workshop on Selected Areas in Cryptography (SAC '98), Queen's University, Kingston, Ontario, Canada
19 htttp://www.stitec.com/