• 대한전자공학회논문지SD
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• 제40권7호
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• pp.526-531
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• 2003

최근 들어, 테스트 시간과 하드웨어의 축소를 위한 많은 내장형 자체 테스트 구조가 연구되고 있다. 대부분의 패턴 생성에 대한 내장형 자체 데스트 구조는 결정 패턴 생성을 위한 것이다. 본 논문에서는 테스트시간과 하드웨어 오버헤드를 줄일 수 있는 새로운 의사 임의 패턴 내장형 자체 테스트 기법을 제안한다 본문에서는 의사 임의 패턴 내장형 자체 테스트 기법의 하드웨어 오버헤드의 축소 가능성에 대한 이론을 간단한 예제와 함께 설명하고 실험 결과를 통해 기존의 방법에 비하여 제안하는 방식을 이용할 경우 하드웨어 오버헤드가 줄어드는 것을 알 수 있으며, 기존의 방법과 제안한 방법의 테스트 시간 비교를 보여 준다.

• 융합보안논문지
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• 제18권4호
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• pp.11-17
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• 2018

최근 하드웨어 키로거는 키보드 내부에 설치할 수 있는 작은 크기와 Wi-Fi 기능을 내장하고 있는 다양한 모듈식 키로거 제품들이 유통되고 있다. 이러한 키로거는 제3자에 의해서 악의적인 목적으로 사용될 경우 탐지가 어려워 정부와 군, 기업과 개인의 중요정보와 민감정보가 유출될 가능성이 높지만, 소프트웨어 키로거와 달리 대응 보안 솔루션과 탐지 방법에 대한 연구가 미흡한 실정이다. 따라서 본 논문에서는 하드웨어 키로거에 의한 보안 취약점과 기존 연구된 탐지 방법들을 살펴보고 키보드의 소비전력, 적외선 온도, X-RAY, 무게, 전자파 등의 비파괴 측정 방법을 통해 모듈식 하드웨어 키로거의 탐지 가능성을 향상 시킬 수 있는 방법을 실험 결과와 함께 제안한다.

• 전기학회논문지
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• 제57권6호
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• pp.951-958
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• 2008

This paper describes development of hardware simulator for the PMSG wind power system, which was designed considering wind characteristic, blade characteristic and blade inertia compensation. The simulator consists of three major parts, such as wind turbine model using induction motor, PMSG generator, converter-inverter set. and control system. The turbine simulator generates torque and speed signals for a specific wind turbine with respect to given wind speed. This torque and speed signals are scaled down to fit the input of 2kW PMSG. The PMSG-side converter operates to track the maximum power point, and the grid-side inverter controls the active and reactive power supplied to the grid. The operational feasibility was verified by computer simulations with PSCAD/EMTDC, and the implementation feasibility was confirmed through experimental works with a hardware set-up.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2645-2648
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• 2003

In this paper, real-time and reconfiguable hardware filter for face recognition is proposed and implemented on FPGA chip using verilog-HDL. In general, face recognition is considerably difficult because it is influenced by noises or the variation of illumination. Some of the commonly used filters such s histogram equalization filter, contrast stretching filter for image enhancement and illumination compensation filter are proposed for realizing more effective illumination compensation. The filter proposed in this paper was designed and verified by debugging and simulating on hardware. Experimental results show that the proposed filter system can generate selective set of real-time reconfiguable hardware filters suitable for face recognition in various situation.

• Journal of Computing Science and Engineering
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• 제11권2호
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• pp.69-77
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• 2017

Recent GPUs have adopted cache memory to benefit general-purpose GPU (GPGPU) programs. However, unlike CPU programs, GPGPU programs typically have considerably less temporal/spatial locality. Moreover, the L1 data cache is used by many threads that access a data size typically considerably larger than the L1 cache, making it critical to bypass L1 data cache intelligently to enhance GPU cache performance. In this paper, we examine GPU cache access behavior and propose a simple hardware-based GPU cache bypassing method that can be applied to GPU applications without recompiling programs. Moreover, we introduce a hybrid method that integrates static profiling information and hardware-based bypassing to further enhance performance. Our experimental results reveal that hardware-based cache bypassing can boost performance for most benchmarks, and the hybrid method can achieve performance comparable to state-of-the-art compiler-based bypassing with considerably less profiling cost.

• Journal of Power Electronics
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• 제10권5호
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• pp.555-562
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• 2010

This paper presents the development of a hardware simulator for a 3-parallel grid-connected PMSG wind power system. With the development of permanent magnetic materials in recent years, the capacity of a PMSG based wind turbine system, which requires a full-scale power converter, has been raised up to a few MW. Since it is limited by the available semiconductor technology, such large amounts of power cannot be delivered with only one power converter. Hence, a parallel connecting technique for converters is required to reduce the ratings of the converters. In this paper, a hardware simulator with 3-parallel converters is described and its control issues are presented as well. Some experimental results are given to illustrate the performance of the simulator system.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2014년도 추계학술대회
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• pp.10-11
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• 2014

In a 2-dimensional (2D) Discrete Cosine Transform (DCT) hardware, a significant fraction of the total hardware area is contributed by the combinational logic used to perform 1-dimensional (2D) transform. The size of the non-combinational logic i.e. the transpose memory is dictated by the size of the largest transform supported. Hence, the optimization of hardware area is performed mainly for 1D-transform combinational logic. This paper demonstrates the use of Multiple Constant Multiplication (MCM) algorithm to reduce the combinational logic area. Partial optimizations are also described for the cases where the direct use of MCM algorithm doesn't meet the timing constraint. Experimental results show that 46% improvement in gate count is achieved for 32 point 1D DCT transform logic after using MCM optimization.

• Journal of Astronomy and Space Sciences
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• 제25권4호
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• pp.347-360
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• 2008

In this paper, a Hardware-In-the-Loop simulator to simulate attitude control of space craft using momentum wheels is developed. The simulator consists of a spherical air bearing system allowing rotation and tilt in all three axes, three momentum wheels for actuation, and an AHRS (Attitude Heading Reference System). The simulator processes various types of data in PC104 and wirelessly communicates with a host PC using TCP/IP protocol. A simple low-cost momentum wheel assembly set and its drive electronics are also developed. Several experiments are performed to test the performance of the momentum wheels. For the control performance test of the simulator, a PID controller is implemented. The results of experimental demonstrations confirm the feasibility and validity of the Hardware-In-the-Loop simulator developed in the current study.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권2호
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• pp.86-93
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• 2004

The DCT algorithm needs an efficient hardware architecture to compute inner product. The conventional design method, like ROM-based DA(Distributed Arithmetic), has large hardware complexity. Because of this reason, a CSHM(Computation Sharing Multiplication) was proposed for implementing inner product by Park. However, the Park's CSHM has inefficient hardware architecture in the precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we presents the optimization design method for inner product using CSHM algorithm and applied it to implementation of 1-D DCT processor. The experimental results show that the proposed multiplier is more efficient than Park's when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using proposed design method is more high performance than typical methods.

• 한국통신학회논문지
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• 제22권3호
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• pp.454-468
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• 1997

This paper presents a bitwidth optimization algorithm for efficient hardware sharing in digital signal processing system. The proposed algorithm determines the fixed-point representation for each signal through bitwidth optimization to generate the hardware requiring less area. To reduce the operator area, the algorithm partitions the abstract operations in the design description into several groups, such that the operations in the same group can share an operator. The partitioning result are fed to a high-level synthesis system to generate the pipelined fixed-point datapaths. The proposed algorithm has been implemented in SODAS-DSP an automatic synthesis system for fixed-point DSP hardware. Accepting the models of DSP algorithms in schematics, the system automatically generates the fixed-point datapath and controller satisfying the design constraints in area, speed, and SNR(Signal-to-Noise Ratio). Experimental results show that the efficiency of the proposed algorithm by generates the area-efficient DSP hardwares satisfying performance constraints.