• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.21-28
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• 1993

Decoding algorithm of noncyclic Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to solve error-values. There is a decoding method by which the computation of both error-location polynomial and error-evaluator polynimial can be avoided in conventional decoding methods using Euclid algorithm. The disadvantage of this method is that the same amount of computation is needed that is equivalent to solve the avoided polynomial. This paper considers the division method on polynomial on GF(2$^{m}$) systematically. And proposes a novel method to find error correcting polynomial by simple mathematical expression without the same amount of computation to find the two avoided polynomial. Especially. proposes the method which the amount of computation to find F (x) from the division M(x) by x, (x-1),....(x--${\alpha}^{n-2}$) respectively can be avoided. By applying the simple expression to decoding procedure on RS codes, propses a new decoding algorithm, and to show the validity of presented method, computer simulation is performed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.2
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• pp.93-106
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• 1998

RS부호의 복호 기법은 전체 통신 시스템의 성능 및 복잡도에 큰 영향을 미친다. 지금까지 RS부호의 복호 기법은 다양한 방법에 있으나Euclid알고리즘과 변환복호기법을 이용한 복호 기법은 오류정정능력이 큰 복호 기법으로 널리 적용되고 있다. 본 논문에서는 오류정정능력이 5이상인 RS부호의 복호 알고리즘에 적용될 수 있는 효율적인 복호 알고리즘을 제시하고, 이를 이용하여 5중 오류 정정(31, 21)RS 부호기 및 복호기를 설계하고VHDL을 사용한 컴퓨터 시뮬레션을 통해서 그 타당성을 검증하였다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.281-284
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk with double error detecting and correcting capability. A variety of error correction codes(ECCs) have been used in magnetic recordings, and optical recordings. Among the various types of ECCs, Reed Solomon(RS) codes has emerged as one the most important ones. The most complex circuit in the RS decoder is the part for finding the error location numbers by solving error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid's algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and peformed logic synthesis using the SYNOPSYS CAD tool. The total umber of gate is about 11,000 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9C
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• pp.876-883
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• 2003

In this paper, we propose an algorithm for organ recognition in ultrasound images using log power spectrum. The main procedure of the algorithm consists of feature extraction and feature classification. In the feature extraction, as a translation invariant feature, log power spectrum is used for extracting the information on echo of the organs tissue from a preprocessed input image. In the feature classification, Mahalanobis distance is used as a measure of the similarity between the feature of an input image and the representative feature of each class. Experimental results for real ultrasound images show that the proposed algorithm yields the improvement of maximum 30% recognition rate than the recognition algorithm using power spectrum and Euclidean distance, and results in better recognition rate of 10-40% than the recognition algorithm using weighted quefrency complex cepstrum.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.966-973
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• 2000

In this paper, we propose a novel RS decoder design yielding smallr circuit size shorter coding latency. The proposed architecture of RS decoder has the following two features. First, circuit size reduced by using Euclid algorithm with mutual operation between cells. Second, coding latency is reduced by using higher frequency than syndrome and error value calculation block. We performed simulation with C language and MATLAB in order to verify the decoding algorithm and implemented using FPGA chips in VHDL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3A
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• pp.231-237
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• 2010

Multi-input multi-output (MIMO) systems are used to improve the transmission rate in proportion to the number of antennas. However, their computational complexity is very high for the detection in the receiver. The sphere decoding (SD) is a detection algorithm with reduced complexity. In this paper, an improved Schnorr-Euchner SD (SE SD) is proposed based on the minimum mean square error (MMSE) and the Euclidean distance criteria without additional complexity.