• Korean Journal of Materials Research
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• v.20 no.1
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• pp.25-30
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• 2010

Si nanowire/multiwalled carbon nanotube nanocomposite arrays were synthesized. Vertically aligned Si nanowire arrays were fabricated by Ag nanodendrite-assisted wet chemical etching of n-type wafers using $HF/AgNO_3$ solution. The composite structure was synthesized by formation of a sheath of carbon multilayers on a Si nanowire template surface through a thermal CVD process under various conditions. The results of Raman spectroscopy, scanning electron microscopy, and high resolution transmission electron microcopy demonstrate that the obtained nanocomposite has a Si nanowire core/carbon nanotube shell structure. The remarkable feature of the proposed method is that the vertically aligned Si nanowire was encapsulated with a multiwalled carbon nanotube without metal catalysts, which is important for nanodevice fabrication. It can be expected that the introduction of Si nanowires into multiwalled carbon nanotubes may significantly alter their electronic and mechanical properties, and may even result in some unexpected material properties. The proposed method possesses great potential for fabricating other semiconductor/CNT nanocomposites.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.365-370
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• 1998

We studied a electrical properties in GaAs/AlGaAs/InGaAs pseudomorphic high electron mobility transistors(PHEMT s) recessed by electron cyclotron resonance(ECR) plasma and wet etching. Using the $NH_4OH$ solution, a nonvolatile AlF$_3$layer formed on AlGaAs surface after selective gate recess is effectively eliminated. Also, we controlled threshold voltage($V_th$) using $H_3PO_4$ etchant. We have fabricated a device with 540 mS/mm maximum transconductance and -0.2 V threshold voltage by using $NH_4OH$ and $H_3PO_4$dip after ECR gate recessing. In a 2-finger GaAs PHEMT with a gate length of 0.2$\mu m$ and width of 100 $\mu m$, a current gain of 15 dB at 10 GHz and a maximum cutoff frequency of 58.9 GHz have been obtained from the measurement of current gain as a function of frequency at 12mA $I_{dss}$ and 2 V souce-drain voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.146-149
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• 2004

Porous silicon(PS) as an excellent light diffuser can be used as an antireflection layer without other antireflection coating(ARC) materials. PS layers were obtained by electrochemical etching(ECE) anodization of silicon wafers in hydrofluoric acid/ethanol/de-ionized(DI) water solution($HF/EtOH/H_2O$). This technique is based on the selective removal of Si atoms from the sample surface forming a layer of PS with adjustable optical, electrical, and mechanical properties. A PS layer with optimal ARC characteristics was obtained in charge density (Q) of 5.2 $C/cm^2$. The weighted reflectance is reduced from 33 % to 4 % in the wavelength between 400 and 1000 nm. The weighted reflectance with optimized PS layers is much less than that obtained with a commercial SiNx ARC on a potassium hydroxide(KOH) pre-textured multi-crystalline silicon(mc-Si) surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.66-66
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• 2007

Lead zirconate titanate (PZT) is one of the most attractive perovskite-type materials for ferroelectric random access memory (FRAM) due to its higher remanant polarization and the ability to withstand higher coercive fields. We first applied the damascene process using chemical mechanical polishing (CMP) to fabricate the PZT thin film capacitor to solve the problems of plasma etching including low etching profile and ion charging. The $0.8{\times}0.8\;{\mu}m$ square patterns of silicon dioxide on Pt/Ti/$SiO_2$/Si substrate were coated by sol-gel method with the precursor solution of PZT. Damascene process by CMP was performed to pattern the PZT thin film with the vertical sidewall and no plasma damage. The polarization-voltage (P-V) characteristics of PZT capacitors and the current-voltage characteristics (I-V) were examined by change of process parameters. To examine the CMP induced damage to PZT capacitor, the domain structure of the polished PZT thin film was also investigated by piezoresponse force microscopy (PFM).

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.189-194
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• 2011

Si-cell was prepared with various types owing to the etching times textured by the KOH etching solution. The pn junction for solar cell was prepared on p-type Si wafer by the furnace using the $POCl_3$ and oxygen mixed precursor, and the metalization was done using by the Al back electrode and Ag front electrode. Textured Si surface was etched by the pyramid formation. The efficiency and the fill factor was increased in the Si-cell with a large size of pyramids, because of the series resistances decrease depending on the increasing of the photon absorbance. Increasing of the absorbance occurred the induction of the short current and open voltage, and then the efficiency was increased.

• Korean Journal of Metals and Materials
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• v.47 no.11
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• pp.748-753
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• 2009

The surface morphology and the surface roughness of n-type SiC induced by wet-treatment using 45% KOH and buffered oxide etchant (BOE-1HF : $6H_2O$) were investigated by atomic force microscopy (AFM). While Si-face of SiC could be etched by alkali solutions such as KOH, acidic solutions such as BOE were hardly able to etch SiC. When the rough SiC samples were used, the surface roughness of etched sample was decreased after wet-treatment regardless of etchant, due to the planarization the of surface by widening of scratches formed by mechanical polishing. It was observed that the initial etching was affected by the energetically unstable sites, such as dangling bond and steps. However, when a relatively smooth sample was used, the surface roughness was rapidly increased after treatment at $180^{\circ}C$ for 1 hr and at room temperature for 4 hr by using KOH solution, resulting from the nano-sized structures such as pores and bumps. This indicates that porous SiC surface can be achieved by using purely chemical treatment.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.125-129
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• 2022

The current display technology tends to be highly integrated with high resolution, the element size is gradually downsized, and the structure becomes complicated. Inductively coupled plasma (ICP) dry etcher of various types of etching equipment is a structure that places a large multi-divisional antenna source on the top lid, passes current to the Antenna, and generates plasma using the induced magnetic field generated at this time. However, in the case of a device of a large area size, a support that can withstand a load structurally is necessary, and when these support portions are applied, arrangement of antenna becomes difficult, which causes reduction in uniformity. As described above, the development of antenna source of a large area having a uniform plasma density on the whole surface is difficult to restrict hardware (H/W). As a solution to this problem, we confirmed the change in uniformity of plasma by applying two kinds of specific shape faraday shield(FICP) to the lower part of the large area upper lid antenna of 6 and 8th more than that generation size. In this thesis, we verify the faraday shield effect which can improve plasma uniformity control of ICP dry etcher equipment applied to medium and large displays.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.6
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• pp.483-489
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• 2014

In this study, experiments were conducted for micro pattern printing to combine solution atomization process and stencil printing based on electrospray deposition. The stencil mask fabricated by etching the photosensitive glass placed below 0.3 mm distance to substrate has 100 um line width. The process parameters of electrospray deposition system for the atomization of the solution are applied voltage and supply flow rate of the solution. Meniscus angle of cone-jet was optimized by varying the supply flow rate from 0.3 ml/hr to 0.7 ml/hr. Voltage condition was verified having symmetric cone-jet angle and no pulsation at 8.5 kV applied voltage. In addition, a number of micro patterns are printed using a single 1 step process by solution atomization process. Variable line width of approximate 100 um was confirmed by changing conditions of solution atomization regardless of the pattern size of stencil mask.

• Clean Technology
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• v.13 no.4
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• pp.274-280
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• 2007

A liquid-liquid solvent extraction process was developed in this study to recover Fe and Ni from heavily concentrated aqueous ferric chloride solution, in an effort to substitute the conventional iron reduction method. Solvent composition and extraction conditions were first developed from the laboratory experiments, and the pilot system was designed and built for commercialization. Stage numbers for extraction and stripping were determined from pilot plant runs, and other operation data were obtained for mass production.

• 한국태양에너지학회:학술대회논문집
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• 2009.11a
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• pp.383-387
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• 2009

Multi-crystalline silicon surface etching without grain-boundary delineation is a challenging task for the fabrication of high efficiency solar cell. The use of sodium hydroxide - sodium hypochlorite (NaOH40% + NaOCl 12%) solution for texturing multi-crystalline silicon wafer surface in solar cell fabrication line is reported in this article. in light current-voltage results, the cells etched in NaOH 40% + NaOCl 12% = 1:2 exhibited higher short circuit current and open circuit voltage than those of the cells etched in NaOH 40% + NaOCl 12% = 1:1 solution. we have obtained 15.19% conversion efficiency in large area(156cm2) multi-Si solar cells etched in NaOH 40% + NaOCl 12% = 1:1 solution.