• Journal of the Korean Ceramic Society
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• v.46 no.1
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• pp.30-34
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• 2009

A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.414-414
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• 2009

나노스피어 리소그래피는 기존의 리소그래피 방법에 비해 나노 크기 패턴을 제작하는데 공정이 간단하며 재현성있게 대면적에 패터닝이 가능하다는 장점이 있다. 본 연구에서는 Vertical LED(V-LED)의 External quantum efficiency 향상을 위하여 나노스피어 리소그래 피를 이용하여 V-LED의 n-GaN 표면을 패터닝을 하였다. n-GaN 위에 Sputter를 이용하여 $SiO_2$를 증착 후 나노스피어를 스핀 코팅을 이용하여 단일막을 형성하였다. 그 후, 반응성 이온 식각 장치를 이용하여 나노스피어의 크기를 조절하고 $SiO_2$층을 식각하였다. 다음과 같은 공정 후 $SiO_2$층을 Mask층으로 하여 n-GaN 표면을 식각하였다. 실험 결과 나노스피어 리소그래피를 이용하여 V-LED의 External quantum efficiency 향상을 위한 n-GaN 표면의 패턴 제작이 가능함을 확인할 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.419-420
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• 2009

The authors fabricated the nanostructural patterns on the surface of SiN antireflection layer of polycrystalline Si solar cell and the surface of crystalline Si wafer using anodic aluminum oxide (AAO) masks in an inductively coupled plasma(ICP) etching process. The AAO nanopattern mask has the hole size of about 70~80nm and an ave rage lattice constant of 100nm. The transferred nano-patterns were observed by the scanning electron microscope (SEM) and the enhancement of solar cell efficiency will be presented.

• 전기의세계
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• v.27 no.4
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• pp.45-51
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• 1978

A new method of realizing the field effect transistor with a sub-.mu. channel width is described. The sub-.mu. channel width is made possible by etching grooves into n$^{+}$ pn$^{[-10]}$ n$^{[-10]}$ structure and using p region at the wall for the channel region of the Metal-Oxide-Semiconductor transistor (MOST), or by diffusing two different types of impurities through the same diffusion mask and using p region at the surface for the channel region of MOST. When the drain voltage is increased at the pn$^{[-10]}$ drainjunction the depletion layer extends into the n$^{[-10]}$ region instead of into p region; this is also the secret of success to realize the sub-.mu. channel width. As the result of the experimental fabrication, a microwave MOST was obtained. The cut-off frequency was calculated to be 15.4 GHz by Linvill's power equation using the measured capacitances and transconductance.

• Journal of the Korean Vacuum Society
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• v.7 no.s1
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• pp.167-170
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• 1998

To apply diamond films in microelectromechanical systems(MEMS), it is necessary to develop the patterning technologies of diamond films in the micrometer scale. In this paper, three different kinds of technologies for patterning CVD diamond films carried out by us were demonstrated: selective growth by improved diamond nucleation in DC bias-enhanced microwave plasma chemical vapor deposition (MPCVD) system, selective growth of seeding using diamond-particle-mixed photoresist, and selective etching of oxygen ion beam using Al as the mask. It was show that high selectivity and precise patterns had been achieved, and all the processes were compatible with IC process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.

• Journal of Magnetics
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• v.13 no.2
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• pp.53-56
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• 2008

This study proposes a simple nano-patterning process for the fabrication of magnetic nanodot arrays on a large area substrate. Ni nanodots were fabricated on a large area (4 inches in diameter) Si substrate using the soft lithographic technique using self-assembled surface micelles of Polystyrene-block-Poly(methyl methacrylate) (PS-b-PMMA) diblock copolymer formed at the air/water interface as a mask. The hexagonal array of micelles was successfully transferred to a Ni thin film on a Si substrate using the Langmuir-Blodgett technique. After ion-mill dry etching, a magnetic Ni nanodot array with a regular hexagon array structure was obtained. The Ni nanodot array showed in-plane easy axis magnetization and typical soft magnetic properties.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.907-912
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• 2005

Micro-patterns of $Pb(Zr_{0.53}Ti_{0.47})O_3$, PZT, thin films with a MPB composition were deposited on $Pt/Ti/SiO_2/Si$ substrate from molecular-designed PZT precursor solution by using self-assembledmonolayer(SAM) as a template. This method includes deposition of SAM followed by the optical etching by exposing the SAM to the UV-light, leading to the patterned SAM as a selective deposition template. The pattern of SAM was formed by irradiating UV-light to the SAM on a substrate and/or patterned PZT thin film through a metal mask for the selective deposition of patterned PZT or lanthanum nickel oxide (LNO) precursor films from alkoxide-based precursor solutions. As a result, patterned ferroelectric PZT and PZT/LNO thin film capacitors with good electrical properties in micrometer size could be successfully deposited.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1069-1072
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• 2003

Ultraviolet-nanoimprint lithography (UV-NIL) is a promising nanoimprint method for cost-effectively defining nanometer scale structures at room temperature and low pressure. Nanostamp fabrication technology is a key technology for UV-NIL because fabricating a high resolution nanostamp is the first step for defining high resolution nanostructures in a substrate. We used quartz as an UV transparent stamp material for the UVNIL. A $5{\times}5{\times}0.09$ inch stamp was fabricated using the quartz etch process in which Cr film was used as a hard mask for transferring nanostructures into the quartz. In this paper, we describe the quartz etching process and discuss the results including SEM images.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1060-1063
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• 2001

The mechanical etching technique has recently been developed to a powder blasting technique for various materials, capable of producing micro structures larger than 100$\mu$m. This paper describes the performance of powder blasting technique in micro-pocketing of stainless steel and the effect of the number of nozzle scanning and the nozzle height on the depth and width of pockets. Experimental results showed that increasing the no. of nozzle scanning and decreasing the nozzle height resulted in the increase of depth and width in pockets. Increase of width results from wear of mask film.