• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.280-285
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• 2003

The influence of silicon surface damage on nickel-silicide (NiSi) has been characterized and H$_2$ anneal and TiN rapping has been applied to suppress the electrical, morphological deterioration phenomenon incurred by the surface damage. The substrate surface is intentionally damaged using Ar IBE (Ion beam etching) which can Precisely control the etch depth. The sheet resistance of NiSi increased about 18% by the surface damage, which is proven to be mainly due to the reduced silicide thickness. It is shown that simultaneous application of H: anneal and TiN capping layer is highly effective in suppressing the surface damage effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.12 no.1
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• pp.27-34
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• 1999

We investigated the effect of mechanical back side damage in viewpoint of electrical and surface morphological characteristics in Czochralski silicon wafer. The intensity of mechanical damage was evaluated by minority carrier recombination lifetime by laser excitation/microwave reflection photoconductance decay technique, atomic force microscope, optical microscope, wet oxidation/preferential etching methods. The data indicate that the higher the mechanical damage degree, the lower the minority carrier lifetime, and surface roughness, damage depth and density of oxidation induced stacking fault increased proportionally.

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.217-224
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• 2011

of materials and simplification of process. Micro-blasting is one of the promising method for recycling of waste wafer due to their simple and low cost process. Therefore, in this paper, we make recycling wafer through the micro-blaster. A surface etched by micro-blaster forms particles, cracks and pyramid structure. A pyramid structure formed by micro-blaster has a advantage of reflectivity decrease. However, lifetime of minority carrier is decreased by particles and cracks. In order to solve this problems, we carried out the DRE(Damage Romove Etching). There are two ways to DRE process ; wet etching, dry etching. After the DRE process, we measured reflectivity and lifetime of minority carrier. Through these results, we confirmed that a wafer recycled can be used in solar cell.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.58-61
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• 2002

SBT thin films were etched at different content of Cl$_2$in Cl$_2$/Ar plasma. We obtained the maximum etch rate of 883 ${\AA}$/min at Cl$_2$(20%)/Ar(80%). As Cl$_2$ gas increased in Cl$_2$/Ar plasma, the etch rate decreased. The maximum etch rate may be explained by variation of volume density for Cl atoms and by the concurrence of two etching mechanisms such as physical sputtering and chemical reaction with formation of low-volatile products, which can be desorbed only by ion bombardment. The variation of volume density for Cl, F and Ar atoms and ion current density were measured by the optical emission spectroscopy and Langmuir probe. To evaluate the physical damage due to plasma, X-ray diffraction and atomic force microscopy analysis carried out. After etching process, P-E hysteresis loops were measured by ferroelectric workstation.

• Progress in Superconductivity
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• v.3 no.2
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• pp.168-171
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• 2002

We have demonstrated ramp-edge Josephson junctions using high temperature superconductors without depositing artificial barriers. We fabricated a surface barrier formed naturally during an ion beam etching process and the annealing under the oxygen atmosphere. The experimental results imply that the barrier natures such as the resistivity are varied by the annealing conditions and the ion milling conditions including the beam voltages. Thus, the ann eating and etching conditions should be optimized to obtain excellent junction properties. In optimizing the fabricating factors, the interface-controlled junctions showed resistively shunted junctions like current-voltage characteristics and an excellent uniformity. These junctions exhibited a spread ($1\sigma$) of $I_{c}$ is 10% fur chips containing 7 junctions at 50K.K.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.130-136
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• 2002

Device makers want to make higher density chips as devices shrink, especially WSix poly stack down is one of the key issues. However, EPD (End Point Detection) time delay was happened in DPS+ poly chamber which is a barrier to achieve device shrink because EPD time delay killed test pattern and next generation device. To investigate the EPD time delay, a test was done with patterned wafers. This experimental was carried out combined with OES(Optical Emission Spectroscopy) and SEM (Scanning Electron Microscopy). OES was used to find corrected wavelength in WSix stack down gate etching. SEM was used to confirm WSix gate profile and gate oxide damage. Through the experiment, a new wavelength (252nm) line of plasma is selected for DPS+ chamber to call correct EPD in WSix stack down gate etching for current device and next generation device.

• Journal of the Optical Society of Korea
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• v.18 no.3
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• pp.283-287
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• 2014

Square lattice nano-hole arrays with diameters and periodicities of 200 and 500 nm, respectively, are fabricated on InGaN/GaN blue light emitting diodes (LEDs) using electron-beam lithography and inductively coupled plasma reactive ion etching processes. Cathodoluminescence (CL) investigations show that light emission intensity from the LEDs with the nano-hole arrays is enhanced compared to that from the planar sample. The CL intensity enhancement factor decreases when the nano-holes penetrate into the multiple quantum wells (MQWs) due to the plasma-induced damage and the residues. Wet chemical treatment using KOH solution is found to be an effective method for light extraction from the nano-patterned LEDs, especially, when the nano-holes penetrate into the MQWs. About 4-fold CL intensity enhancement factor is achieved by the KOH treatments after the dry etching for the sample with a 250-nm deep nano-hole array.

• Korean Journal of Materials Research
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• v.27 no.8
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• pp.397-402
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• 2017

We used an etching process to control the line-width of screen printed Ag paste patterns. Ag paste was printed on anodized Al substrate to produce a high power LED. In general, Ag paste spreads or diffuses on anodized Al substrate in the process of screen printing; therefore, the line-width of the printed Ag paste pattern increases in contrast with the ideal line-width of the pattern. Smudges of Ag paste on anodized Al substrate were removed by neutral etching process without surface damage of the anodized Al substrate. Accordingly, the line-width of the printed Ag paste pattern was controlled as close as possible to the ideal line-width. When the etched Ag paste pattern was used as a seed layer for electroless Ni plating, the line width of the plated Ni film was similar to the line-width of the etched Ag paste pattern. Finally, in pattern formation by Ag paste screen printing, we found that the accuracy of the line-width of the pattern can be effectively improved by using an etching process before electroless Ni plating.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.9 s.186
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• pp.164-173
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• 2006

The cooling capacity of a micro-heat pipe is mainly governed by the magnitude of capillary pressure induced in the wick structure. For microchannel wicks, a higher capillary pressure is achievable for narrower and deeper channels. In this study, a metallic micro-heat pipe adopting high-aspect-ratio microchannel wicks is fabricated. Micromachining of high-aspect-ratio microchannels is done using the laser-induced wet etching technique in which a focused laser beam irradiates the workpiece placed in a liquid etchant along a desired channel pattern. Because of the direct writing characteristic of the laser-induced wet etching method, no mask is necessary and the fabrication procedure is relatively simple. Deep microchannels of an aspect ratio close to 10 can be readily fabricated with little heat damage of the workpiece. The laser-induced wet etching process for the fabrication of high-aspect-ratio microchannels in 0.5mm thick stainless steel foil is presented in detail. The shape and size variations of microchannels with respect to the process variables, such as laser power, scanning speed, number of scans, and etchant concentration are closely examined. Also, the fabrication of a flat micro-heat pipe based on the high-aspect-ratio microchannels is demonstrated.