• 제목/요약/키워드: etch selectivity

검색결과 224건 처리시간 0.034초

Prediction of plasma etching using genetic-algorithm controlled backpropagation neural network

  • Kim, Sung-Mo;Kim, Byung-Whan
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2003년도 ICCAS
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    • pp.1305-1308
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    • 2003
  • A new technique is presented to construct a predictive model of plasma etch process. This was accomplished by combining a backpropagation neural network (BPNN) and a genetic algorithm (GA). The predictive model constructed in this way is referred to as a GA-BPNN. The GA played a role of controlling training factors simultaneously. The training factors to be optimized are the hidden neuron, training tolerance, initial weight magnitude, and two gradients of bipolar sigmoid and linear functions. Each etch response was optimized separately. The proposed scheme was evaluated with a set of experimental plasma etch data. The etch process was characterized by a $2^3$ full factorial experiment. The etch responses modeled are aluminum (A1) etch rate, silica profile angle, A1 selectivity, and dc bias. Additional test data were prepared to evaluate model appropriateness. The GA-BPNN was compared to a conventional BPNN. Compared to the BPNN, the GA-BPNN demonstrated an improvement of more than 20% for all etch responses. The improvement was significant in the case of A1 etch rate.

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BLT 박막의 건식 식각 특성에 관한 연구 (Dry Etching Characteristics of BLT Thin Film)

  • 김동표;김창일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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    • pp.309-311
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    • 2003
  • The effects of etch parameters on dry etching of BLT thin films were investigated with ICP etch system in $Cl_2$/Ar and $BCl_2/Cl_2$/Ar gas. The etch rate and etch selectivity of BLT films were examined as a function of gas concentration, ICP power, bias power, and pressure. The maximum etch rates of 191.1 nm/min was obtained at the mixed etch condition of $BCl_3(20%)/Cl_2$/Ar, 700 W ICP RF power, 12 mTorr pressure and 400 W substrate RF power. As ICP power and rf power increased, the etch rate of BLT increased. As pressure increased, the etch rate of BLT decreased. The changes of radicals in both $Cl_2$/Ar and $BCl_3/Cl_2$/Ar plasma were measured with using optical emission spectroscopy (OES).

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학습과 예측의 유전 제어: 플라즈마 식각공정 데이터 모델링에의 응용 (Genetic Control of Learning and Prediction: Application to Modeling of Plasma Etch Process Data)

  • 우형수;곽관웅;김병환
    • 제어로봇시스템학회논문지
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    • 제13권4호
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    • pp.315-319
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    • 2007
  • A technique to model plasma processes was presented. This was accomplished by combining the backpropagation neural network (BPNN) and genetic algorithm (GA). Particularly, the GA was used to optimize five training factor effects by balancing the training and test errors. The technique was evaluated with the plasma etch data, characterized by a face-centered Box Wilson experiment. The etch outputs modeled include Al etch rate, AI selectivity, DC bias, and silica profile angle. Scanning electron microscope was used to quantify the etch outputs. For comparison, the etch outputs were modeled in a conventional fashion. GABPNN models demonstrated a considerable improvement of more than 25% for all etch outputs only but he DC bias. About 40% improvements were even achieved for the profile angle and AI etch rate. The improvements demonstrate that the presented technique is effective to improving BPNN prediction performance.

Cl2/HBr/O2 고밀도 플라즈마에서 비정질 실리콘 게이트 식각공정 특성 (Characteristics of Amorphous Silicon Gate Etching in Cl2/HBr/O2 High Density Plasma)

  • 이원규
    • Korean Chemical Engineering Research
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    • 제47권1호
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    • pp.79-83
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    • 2009
  • 본 연구에서 고밀도 플라즈마 식각 장치를 사용한 비정질 실리콘 막의 게이트 전극선 형성공정에서 여러 가지 식각 변수가 치수 제어와 식각 속도 및 식각 선택비 등 식각 특성에 미치는 영향을 분석하였다. $Cl_2/HBr/O_2$로 구성된 식각 기체의 전체 유량을 증가시키면 비정질 실리콘의 식각 속도가 증가하나 식각 전후의 형상치수는 변화없이 거의 일정하였다. 전체 유량을 고정시키고 $Cl_2$와 HBr 간의 유량비를 변화시키면 HBr의 유량이 커질수록 비정질 실리콘의 식각 속도가 감소하였다. $O_2$의 유량을 증가시키면 산화막의 식각 속도가 상대적으로 낮아져 식각 선택비를 증가시켜 식각 공정의 안정성을 높이나 게이트 전극선을 경사지게 하는 특성을 보인다. Source power의 증가는 비정질 실리콘 식각 속도의 증가와 더불어 형상치수의 증가를 가져오며, bias power의 증가는 비정질 실리콘과 산화막의 식각 속도를 증가시키나 식각 선택비를 크게 감소시키는 경향을 보였다.

STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화 (Property variation of transistor in Gate Etch Process versus topology of STI CMP)

  • 김상용;정헌상;박민우;김창일;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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    • pp.181-184
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    • 2001
  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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Etch Characteristics of $SiO_2$ by using Pulse-Time Modulation in the Dual-Frequency Capacitive Coupled Plasma

  • 전민환;강세구;박종윤;염근영
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.472-472
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    • 2011
  • The capacitive coupled plasma (CCP) has been extensively used in the semiconductor industry because it has not only good uniformity, but also low electron temperature. But CCP source has some problems, such as difficulty in varying the ion bombardment energy separately, low plasma density, and high processing pressure, etc. In this reason, dual frequency CCP has been investigated with a separate substrate biasing to control the plasma parameters and to obtain high etch rate with high etch selectivity. Especially, in this study, we studied on the etching of $SiO_2$ by using the pulse-time modulation in the dual-frequency CCP source composed of 60 MHz/ 2 MHz rf power. By using the combination of high /low rf powers, the differences in the gas dissociation, plasma density, and etch characteristics were investigated. Also, as the size of the semiconductor device is decreased to nano-scale, the etching of contact hole which has nano-scale higher aspect ratio is required. For the nano-scale contact hole etching by using continuous plasma, several etch problems such as bowing, sidewall taper, twist, mask faceting, erosion, distortions etc. occurs. To resolve these problems, etching in low process pressure, more sidewall passivation by using fluorocarbon-based plasma with high carbon ratio, low temperature processing, charge effect breaking, power modulation are needed. Therefore, in this study, to resolve these problems, we used the pulse-time modulated dual-frequency CCP system. Pulse plasma is generated by periodical turning the RF power On and Off state. We measured the etch rate, etch selectivity and etch profile by using a step profilometer and SEM. Also the X-ray photoelectron spectroscopic analysis on the surfaces etched by different duty ratio conditions correlate with the results above.

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STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화 (Property variation of transistor in Gate Etch Process versus topology of STI CMP)

  • 김상용;정헌상;박민우;김창일;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집
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    • pp.181-184
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    • 2001
  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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기계화학적 연마를 이용한 트렌치 구조의 산화막 평탄화 (Oxide Planarization of Trench Structure using Chemical Mechanical Polishing(CMP))

  • 김철복;김상용;서용진
    • 한국전기전자재료학회논문지
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    • 제15권10호
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    • pp.838-843
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    • 2002
  • Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

Selective etching of SiO2 using embedded RF pulsing in a dual-frequency capacitively coupled plasma system

  • 염원균;전민환;김경남;염근영
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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    • pp.136.2-136.2
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    • 2015
  • 반도체 제조는 chip의 성능 향상 및 단가 하락을 위해 지속적으로 pattern size가 nano size로 감소해 왔고, capacitor 용량은 증가해 왔다. 이러한 현상은 contact hole의 aspect ratio를 지속적으로 증가시킨바, 그에 따라 최적의 HARC (high aspect ratio contact)을 확보하는 적합한 dry etch process가 필수적이다. 그러나 HARC dry etch process는 많은 critical plasma properties 에 의존하는 매우 복잡한 공정이다. 따라서, critical plasma properties를 적절히 조절하여 higher aspect ratio, higher etch selectivity, tighter critical dimension control, lower P2ID과 같은 plasma characteristics을 확보하는 것이 요구된다. 현재 critical plasma properties를 제어하기 위해 다양한 plasma etching 방법이 연구 되어왔다. 이 중 plasma를 낮은 kHz의 frequency에서 on/off 하는 pulsed plasma etching technique은 nanoscale semiconductor material의 etch 특성을 효과적으로 향상 시킬 수 있다. 따라서 본 실험에서는 dual-frequency capacitive coupled plasma (DF-CCP)을 사용하여 plasma operation 동안 duty ratio와 pulse frequency와 같은 pulse parameters를 적용하여 plasma의 특성을 각각 제어함으로써 etch selectivity와 uniformity를 향상 시키고자 하였다. Selective SiO2 contact etching을 위해 top electrode에는 60 MHz pulsed RF source power를, bottom electrode에는 2MHz pulse plasma를 인가하여 synchronously pulsed dual-frequency capacitive coupled plasma (DF-CCP)에서의 plasma 특성과 dual pulsed plasma의 sync. pulsing duty ratio의 영향에 따른 etching 특성 등을 연구 진행하였다. 또한 emissive probe를 통해 전자온도, OES를 통한 radical 분석으로 critical Plasma properties를 분석하였고 SEM을 통한 etch 특성분석과 XPS를 통한 표면분석도 함께 진행하였다. 그 결과 60%의 source duty percentage와 50%의 bias duty percentage에서 가장 향상된 etch 특성을 얻을 수 있었다.

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고밀도 플라즈마에 의한 $Y_2O_3$ 박막의 식각 메커니즘 연구 (Etch Mechanism of $Y_2O_3$ Thin Films in High Density Plasma)

  • 김영찬;김창일;장의구
    • 한국항해항만학회:학술대회논문집
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    • 한국항해항만학회 2000년도 추계학술대회논문집
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    • pp.25.1-28
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    • 2000
  • In this study, $Y_2O_3$ thin films were etched with inductively coupled plasma (ICP). The etch rate of $Y_2O_3$ , and the selectivity of $Y_2O_3$ to YMnO$_3$were investigated by varying $Cl_2$/($Cl_2$+Ar) gas mixing ratio. The maximum etch rate of $Y_2O_3$ , and the selectivity of $Y_2O_3$ to YMnO$_3$ were 302/min, and 2.4 at $Cl_2$/($Cl_2$+Ar) gas mixing ratio of 0.2 repetitively. In x-ray photoelectron spectroscopy (XPS) analysis, $Y_2O_3$ thin film was dominantly etched by Ar ion bombardment, and was assisted by chemical reaction of Cl radical. These results were confirmed by secondary ion mass spectroscopy(SIMS) analysis. YCl, and $YC_3$ existed at 126.03 a.m.u, and 192.3 a.m.u, respectively.

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