• Title/Summary/Keyword: error correction codes

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SEC-DED-DAEC codes without mis-correction for protecting on-chip memories (오정정 없이 온칩 메모리 보호를 위한 SEC-DED-DAEC 부호)

  • Jun, Hoyoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.10
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    • pp.1559-1562
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    • 2022
  • As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

Error correction codes to manage multiple bit upset in on-chip memories (온칩 메모리 내 다중 비트 이상에 대처하기 위한 오류 정정 부호)

  • Jun, Hoyoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.11
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    • pp.1747-1750
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    • 2022
  • As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

Optimum Convolutional Error Correction Codes for FQPSK-B Signals

  • Park, Hyung-Chul
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.5C
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    • pp.611-617
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    • 2004
  • The optimum convolutional error correction codes for recently standardized Feher-patented quadrature phase-shift keying (FQPSK-B) modulation are proposed. We utilize the continuous phase modulation characteristics of FQPSK-B signals for calculating the minimum Euclidean distance of convolutional coded FQPSK-B signal. It is shown that the Euclidean distance between two FQPSK-B signals is proportional to the Hamming distance between two binary data sequence. Utilizing this characteristic, we show that the convolutional codes with optimum free Hamming distance is the optimum convolutional codes for FQPSK-B signals.

MATE: Memory- and Retraining-Free Error Correction for Convolutional Neural Network Weights

  • Jang, Myeungjae;Hong, Jeongkyu
    • Journal of information and communication convergence engineering
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    • v.19 no.1
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    • pp.22-28
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    • 2021
  • Convolutional neural networks (CNNs) are one of the most frequently used artificial intelligence techniques. Among CNN-based applications, small and timing-sensitive applications have emerged, which must be reliable to prevent severe accidents. However, as the small and timing-sensitive systems do not have sufficient system resources, they do not possess proper error protection schemes. In this paper, we propose MATE, which is a low-cost CNN weight error correction technique. Based on the observation that all mantissa bits are not closely related to the accuracy, MATE replaces some mantissa bits in the weight with error correction codes. Therefore, MATE can provide high data protection without requiring additional memory space or modifying the memory architecture. The experimental results demonstrate that MATE retains nearly the same accuracy as the ideal error-free case on erroneous DRAM and has approximately 60% accuracy, even with extremely high bit error rates.

Search Methods for Covering Patterns of CRC Codes for Error Recovery (오류 복구를 위한 CRC 코드 커버링 패턴의 탐색 방법)

  • Sung, Won-Jin
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.4
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    • pp.299-302
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    • 2002
  • Error detection and correction using CRC and the general class of cyclic codes is an important part of designing reliable data transmission schemes. The decoding method for cyclic codes using covering patterns is easily-implementable, and its complexity de-pends on the number of covering patterns employed. Determination of the minimal set of covering patterns for a given code is an open problem. In this paper, an efficient search method for constructing minimal sets of covering patterns is proposed and compared with several existing search methods. The result is applicable to various codes of practical interest.

New Decoding Techniques of RS Codes for Optical Disks (광학식 디스크에 적합한 RS 부호의 새로운 복호 기법)

  • 엄흥열;김재문;이만영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.3
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    • pp.16-33
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    • 1993
  • New decoding algorithm of double-error-correction Reed-Solmon codes over GF(2$^{8}$) for optical compact disks is proposed and decoding algorithm of RS codes with triple-error-correcting capability is presented in this paper. First of all. efficient algorithms for estimating the number of errors in the received code words are presented. The most complex circuits in the RS decoder are parts for soving the error-location numbers from error-location polynomial, so the complexity of those circuits has a great influence on overall decoder complexity. One of the most known algorithm for searching the error-location number is Chien's method, in which all the elements of GF(2$^{m}$) are substituted into the error-location polynomial and the error-location number can be found as the elements satisfying the error-location polynomial. But Chien's scheme needs another 1 frame delay in the decoder, which reduces decoding speed as well as require more stroage circuits for the received ocode symbols. The ther is Polkinghorn method, in which the roots can be resolved directly by solving the error-location polynomial. Bur this method needs additional ROM (readonly memory) for storing tthe roots of the all possible coefficients of error-location polynomial or much more complex cicuit. Simple, efficient, and high speed method for solving the error-location number and decoding algorithm of double-error correction RS codes which reudce considerably the complexity of decoder are proposed by using Hilbert theorems in this paper. And the performance of the proposed decoding algorithm is compared with that of conventional decoding algorithms. As a result of comparison, the proposed decoding algorithm is superior to the conventional decoding algorithm with respect to decoding delay and decoder complexity. And decoding algorithm of RS codes with triple-error-correcting capability is presented, which is suitable for error-correction in digital audio tape, also.

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Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm

  • Park, Kyeongbin;Chung, Ki-Seok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.2
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    • pp.485-499
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    • 2021
  • Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

Energy Savings in OFDM Systems through Cooperative Relaying

  • Khuong, Ho Van;Kong, Hyung-Yun
    • ETRI Journal
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    • v.29 no.1
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    • pp.27-35
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    • 2007
  • Energy savings in orthogonal frequency division multiplexing (OFDM) systems is an active research area. In order to achieve a solution, we propose a new cooperative relaying scheme operated on a per subcarrier basis. This scheme improves the bit error rate (BER) performance of the conventional signal-to-noise ratio (SNR)-based selection relaying scheme by substituting SNR with symbol error probability (SEP) to evaluate the received signal quality at the relay more reliably. Since the cooperative relaying provides spatial diversity gain for each subcarrier, thus statistically enhancing the reliability of subcarriers at the destination, the total number of lost subcarriers due to deep fading is reduced. In other words, cooperative relaying can alleviate error symbols in a codeword so that the error correction capability of forward error correction codes can be fully exploited to improve the BER performance (or save transmission energy at a target BER). Monte-Carlo simulations validate the proposed approach.

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Performance and Energy Consumption Analysis of 802.11 with FEC Codes over Wireless Sensor Networks

  • Ahn, Jong-Suk;Yoon, Jong-Hyuk;Lee, Kang-Woo
    • Journal of Communications and Networks
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    • v.9 no.3
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    • pp.265-273
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    • 2007
  • This paper expands an analytical performance model of 802.11 to accurately estimate throughput and energy demand of 802.11-based wireless sensor network (WSN) when sensor nodes employ Reed-Solomon (RS) codes, one of block forward error correction (FEC) techniques. This model evaluates these two metrics as a function of the channel bit error rate (BER) and the RS symbol size. Since the basic recovery unit of RS codes is a symbol not a bit, the symbol size affects the WSN performance even if each packet carries the same amount of FEC check bits. The larger size is more effective to recover long-lasting error bursts although it increases the computational complexity of encoding and decoding RS codes. For applying the extended model to WSNs, this paper collects traffic traces from a WSN consisting of two TIP50CM sensor nodes and measures its energy consumption for processing RS codes. Based on traces, it approximates WSN channels with Gilbert models. The computational analyses confirm that the adoption of RS codes in 802.11 significantly improves its throughput and energy efficiency of WSNs with a high BER. They also predict that the choice of an appropriate RS symbol size causes a lot of difference in throughput and power waste over short-term durations while the symbol size rarely affects the long-term average of these metrics.

Recent Successive Cancellation Decoding Methods for Polar Codes

  • Choi, Soyeon;Lee, Youngjoo;Yoo, Hoyoung
    • Journal of Semiconductor Engineering
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    • v.1 no.2
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    • pp.74-80
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    • 2020
  • Due to its superior error correcting performance with affordable hardware complexity, the Polar code becomes one of the most important error correction codes (ECCs) and now intensively examined to check its applicability in various fields. However, Successive Cancellation (SC) decoding that brings the advanced Successive Cancellation List (SCL) decoding suffers from the long latency due to the nature of serial processing limiting the practical implementation. To mitigate this problem, many decoding architectures, mainly divided into pruning and parallel decoding, are presented in previous manuscripts. In this paper, we compare the recent SC decoding architectures and analyze them using a tree structure.