• 제목/요약/키워드: epoxy molding compound

검색결과 73건 처리시간 0.022초

리드프레임/EMC 계면의 파괴 인성치 (Fracture Toughness of Leadframe/EMC Interface)

  • 이호영;유진
    • 한국표면공학회지
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    • 제32권6호
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    • pp.647-657
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    • 1999
  • Due to the inherently poor adhesion strength of Cu-based leadframe/EMC (Epoxy Molding Compound) interface, popcorn cracking of thin plastic packages frequently occurs during the solder reflow process. In the present work, in order to enhance the adhesion strength of Cu-based leadframe/EMC interface, black-oxide layer was formed on the leadframe surface by chemical oxidation of leadframe, and then oxidized leadframe sheets were molded with EMC and machined to form SDCB (Sandwiched Double-Cantilever Beam) and SBN (Sandwiched Brazil-Nut) specimens. SDCB and SBN specimens were designed to measure the adhesion strength between leadframe and EMC in terms of critical energy-release rate under quasi-Mode I ($G_{IC}$ ) and mixed Mode loading ($G_{C}$ /) conditions, respectively. Results showed that black-oxide treatment of Cu-based leadframe initially introduced pebble-like X$C_2$O crystals with smooth facets on its surface, and after the full growth of $Cu_2$O layer, acicular CuO crystals were formed atop of the $Cu_2$O layer. According to the result of SDCB test, $Cu_2$O crystals on the leadframe surface did not increase ($G_{IC}$), however, acicular CuO crystals on the $Cu_2$O layer enhanced $G_{IC}$ considerably. The main reason for the adhesion improvement seems to be associated with the adhesion of CuO to EMC by mechanical interlocking mechanism. On the other hand, as the Mode II component increased, $G_{C}$ was increased, and when the phase angle was -34$^{\circ}$, crack Kinking into EMC was occured.d.

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표면실장용 IC 패키지 솔더접합부의 열피로 수명 예측 (A prediction of the thermal fatigue life of solder joint in IC package for surface mount)

  • 윤준호;신영의
    • Journal of Welding and Joining
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    • 제16권4호
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    • pp.92-97
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    • 1998
  • Because of the low melting temperature of solder, each temperature cycle initiates an irrecoverable creep deformation at the solder interconnection which connects the package body with the PCB. The crack starts and propagates from the position where the creep deformation is maximized. This work has tried to compare and analyze the thermal fatigue life of solder interconnection which is affected by the lead material, the size of die pad, chip thickness, and interface delamination of 48-Pin TSOP under the temperature cycle ($0^{\circ}C$~1$25^{\circ}C$). The crack initiation position and thermal fatigue life which are calculated by using FEA method are well matched with the results of experiments. The thermal Fatigue life of copper lead frame is extended around 3.6 times longer than that of alloy 42 lead frame. It is maximized when the chip size is matched with the length of the lead. It tends to be extended as the thickness of chip got thinner. As the interfacial delamination between die pad and EMC is increased, the thermal fatigue life tends to decrease in the beginning of delamination, and increase after the delamination grew after 45% of the length of die pad.

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Thermal Model for Power Converters Based on Thermal Impedance

  • Xu, Yang;Chen, Hao;Lv, Sen;Huang, Feifei;Hu, Zhentao
    • Journal of Power Electronics
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    • 제13권6호
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    • pp.1080-1089
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    • 2013
  • In this paper, the superposition principle of a heat sink temperature rise is verified based on the mathematical model of a plate-fin heat sink with two mounted heat sources. According to this, the distributed coupling thermal impedance matrix for a heat sink with multiple devices is present, and the equations for calculating the device transient junction temperatures are given. Then methods to extract the heat sink thermal impedance matrix and to measure the Epoxy Molding Compound (EMC) surface temperature of the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) instead of the junction temperature or device case temperature are proposed. The new thermal impedance model for the power converters in Switched Reluctance Motor (SRM) drivers is implemented in MATLAB/Simulink. The obtained simulation results are validated with experimental results. Compared with the Finite Element Method (FEM) thermal model and the traditional thermal impedance model, the proposed thermal model can provide a high simulation speed with a high accuracy. Finally, the temperature rise distributions of a power converter with two control strategies, the maximum junction temperature rise, the transient temperature rise characteristics, and the thermal coupling effect are discussed.

반도체 제조 공정에서 발생 가능한 부산물 (Exposure Possibility to By-products during the Processes of Semiconductor Manufacture)

  • 박승현;신정아;박해동
    • 한국산업보건학회지
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    • 제22권1호
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    • pp.52-59
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    • 2012
  • Objectives: The purpose of this study was to evaluate the exposure possibility of by-products during the semiconductor manufacturing processes. Methods: The authors investigated types of chemicals generated during semiconductor manufacturing processes by the qualitative experiment on generation of by-products at the laboratory and a literature survey. Results: By-products due to decomposition of photoresist by UV-light during the photo-lithography process, ionization of arsine during the ion implant process, and inter-reactions of chemicals used at diffusion and deposition processes can be generated in wafer fabrication line. Volatile organic compounds (VOCs) such as benzene and formaldehyde can be generated during the mold process due to decomposition of epoxy molding compound and mold cleaner in semiconductor chip assembly line. Conclusions: Various types of by-products can be generated during the semiconductor manufacturing processes. Therefore, by-products carcinogen such as benzene, formaldehyde, and arsenic as well as chemical substances used during the semiconductor manufacturing processes should be controlled carefully.

혼합하중 조건하에서 갈색산화물이 입혀진 구리계 리드프레임/EMC 계면의 파손경로 (Failure Path of the Brown-oxide-coated Copper-based Leadframe/EMC Interface under Mixed-Mode Loading)

  • 이호영
    • 한국표면공학회지
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    • 제36권6호
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    • pp.491-499
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    • 2003
  • Copper-based leadframe sheets were oxidized in a hot alkaline solution to form brown-oxide layer on the surface and molded with epoxy molding compound (EMC). The brown-oxide-coated leadframe/EMC joints were machined to form sandwiched double-cantilever beam (SDCB) specimens and sandwiched Brazil-nut (SBN) specimens for the purpose of measuring the fracture toughness of leadframe/EMC interfaces. The SDCB and the SBN specimens were designed to measure the fracture toughness of the leadframe/EMC interfaces under nearly mode-I loading and mixed-mode (mode I + mode II) loading conditions, respectively. Fracture surfaces were analyzed by various equipment such as glancing-angle XRD, SEM, AES, EDS and AFM to elucidate failure path. Results showed that failure occurred irregularly in the SDCB specimens, and oxidation time of 2 minutes divided the types of irregular failures into two classes. The failure in the SBN specimens was quite different from that in the SDCB specimens. The failure path in the SBN specimens was not dependent on the phase angle as well as the distance from tips of pre-cracks.

야간 투시 영상시스템의 Green A에 적합한 작은 형태인자를 가진 LED에 관한 연구 (A Study on LED with Small Form Factor Suitable for Green A of Night Vision Imaging System)

  • 김태훈;유창한;윤현주;김민평;윤호신
    • 반도체디스플레이기술학회지
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    • 제20권4호
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    • pp.62-67
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    • 2021
  • In this study, we have successfully developed an unique NVIS Green A compatible LED by combining two technologies. One is white LED made with a black EMC (epoxy molding compound) lead frame. The other is NVIS Green A filter that shields the near infrared region made in the film method. The form factor of the developed NVIS Green A compatible LED was 2.0 × 2.0 × 0.95 mm. And it is possible to satisfy NVIS radiance and color limit specified in MIL-STD-3009 by controlling the concentration of Green A dye and the thickness of the NVIS filter as well as adjusting of color temperature of the white LED. From these results, we are expected that the developed NVIS Green A suitable LED is a promising solution for the weight reduction and the cost reduction of avionic applications.

Brown Oxide 형성이 리드프레임/EMC 계면의 파괴인성치에 미치는 영향 (Effect of Brown Oxide Formation on the Fracture Toughness of Leadframe/EMC Interface)

  • 이호영;유진
    • 한국표면공학회지
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    • 제32권4호
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    • pp.531-537
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    • 1999
  • A copper based leadframe was oxidized in brown-oxide forming solution, then the growth characteristics of brown oxide and the effect of brown-oxide formation on the adhesion strength of leadframe to epoxy molding compound (EMC) were studied by using sandwiched double cantilever beam (SDCB) specimens. The brown oxide is composed of fine acicular CuO, and its thickness increased up to ~150 nm within 2 minutes and saturated. Bare leadframe showed alomost no adhesion to EMC, while once the brown-oxide layer formed on the Surface of leadframe, the adhesion strength increased up to ~80 J/$\m^2$ within 2 minutes. Correlation between oxide thickness, $\delta$ and the adhesion strength in terms of interfacial fracture toughness, $G_{c}$ was linear. Considering the above results, we might conclude that the main adhesion mechanism of brown-oxide treated leadframe to EMC is mechanical interlocking, in which fine acicular CuO plays a major role.e.

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수치해석을 이용한 팬 아웃 웨이퍼 레벨 패키지의 휨 경향 및 신뢰성 연구 (Numerical Analysis of Warpage and Reliability of Fan-out Wafer Level Package)

  • 이미경;정진욱;옥진영;좌성훈
    • 마이크로전자및패키징학회지
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    • 제21권1호
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    • pp.31-39
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    • 2014
  • 최근 모바일 응용 제품에 사용되는 반도체 패키지는 고밀도, 초소형 및 다기능을 요구하고 있다. 기존의 웨이퍼 레벨 패키지(wafer level package, WLP)는 fan-in 형태로, I/O 단자가 많은 칩에 사용하기에는 한계가 있다. 따라서 팬 아웃 웨이퍼 레벨 패키지(fan-out wafer level package, FOWLP)가 새로운 기술로 부각되고 있다. FOWLP에서 가장 심각한 문제 중의 하나는 휨(warpage)의 발생으로, 이는 FOWLP의 두께가 기존 패키지에 비하여 얇고, 다이 레벨 패키지 보다 휨의 크기가 매우 크기 때문이다. 휨의 발생은 후속 공정의 수율 및 웨이퍼 핸들링에 영향을 미친다. 본 연구에서는 FOWLP의 휨의 특성과 휨에 영향을 미치는 주요 인자에 대해서 수치해석을 이용하여 분석하였다. 휨을 최소화하기 위하여 여러 종류의 epoxy mold compound (EMC) 및 캐리어 재질을 사용하였을 경우에 대해서 휨의 크기를 비교하였다. 또한 FOWLP의 주요 공정인 EMC 몰딩 후, 그리고 캐리어 분리(detachment) 공정 후의 휨의 크기를 각각 해석하였다. 해석 결과, EMC 몰딩 후에 발생한 휨에 가장 영향을 미치는 인자는 EMC의 CTE이며, EMC의 CTE를 낮추거나 Tg(유리천이온도)를 높임으로서 휨을 감소시킬 수 있다. 캐리어 재질로는 Alloy42 재질이 가장 낮은 휨을 보였으며, 따라서 가격, 산화 문제, 열전달 문제를 고려하여 볼 때 Alloy 42 혹은 SUS 재질이 캐리어로서 적합할 것으로 판단된다.

반도체 몰딩 공정에서 발생하는 EMC 폐기물의 재활용을 통한 실리카 나노입자의 제조 및 반도체용 CMP 슬러리로의 응용 (Fabrication of Silica Nanoparticles by Recycling EMC Waste from Semiconductor Molding Process and Its Application to CMP Slurry)

  • 김하영;추연룡;박규식;임지수;윤창민
    • 유기물자원화
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    • 제32권1호
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    • pp.21-29
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    • 2024
  • 본 연구에서는 반도체 패키징의 몰딩 공정에서 발생하는 EMC 폐기물을 재활용하여 실리카 나노입자를 성공적으로 제조하였으며, 이를 CMP 공정용 슬러리의 연마재 물질로 응용하였다. 상세히는, EMC 폐기물을 암모니아 용액과 소니케이터를 활용하여 열과 에너지를 가하는 에칭 과정을 통해 실리카 나노입자를 제조하기 위한 실라놀 전구체를 추출하였다. 이후 실라놀 전구체를 활용하여 졸-겔법을 통해 약 100nm를 나타내는 균일한 구형의 실리카 나노입자(e-SiO2, experimentally synthesized SiO2)를 합성하였다. 제조한 e-SiO2는 물리화학적 분석을 통해 상용화된 실리카 입자(c-SiO2, commercially SiO2)와 동일한 형상과 구조를 지니고 있음을 확인할 수 있었다. 최종적으로, e-SiO2를 연마재로 사용하여 CMP 공정용 슬러리를 제조하여 실제적인 반도체 칩의 연마 성능을 확인하였다. 그 결과, 반도체 칩의 표면에 존재하던 스크래치가 성공적으로 제거되어 매끈한 표면으로 바뀌게 된 것을 확인하였다. 본 연구 결과는 물질의 재활용법에 대한 설계를 통해 EMC 폐기물의 부가가치를 향상시키기 위하여 반도체 공정에서 대표적으로 활용되는 고부가가치 소재인 실리카 입자로 성공적으로 제조하고 이를 응용하는 방법에 대해 제시하였다.

탄소섬유를 이용한 열가소성 복합재료 시트 제조 및 특성 (Fabrication and Characterization of the Carbon Fiber Composite Sheets)

  • 이윤선;송승아;김완진;김성수;정용식
    • Composites Research
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    • 제28권4호
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    • pp.168-175
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    • 2015
  • 탄소섬유 강화 복합재료는 높은 비강도 및 비강성을 가지기 때문에 자동차 산업, 선박, 우주 항공 산업과 같은 다양한 산업 분야에 적용되어 왔으며, 수요가 점차 증가하고 있다. 탄소섬유 강화 복합재료에는 기지재로 주로 에폭시(Epoxy)와 같이 점도가 낮고 젖음 특성이 우수하며 강도가 양호한 열경화성(Thermosetting) 수지가 사용된다. 열경화성 수지는 우수한 물리적 특성을 나타내지만 재사용이 어렵다. 이러한 문제를 해결하기 위하여 재사용이 가능한 탄소섬유 강화 열가소성 수지(Thermoplastic) 복합재료 개발 및 탄소섬유 재사용에 관한 많은 연구들이 진행되고 있다. 본 연구에서는 열분해 방법을 사용하여 탄소섬유/에폭시 복합재료로부터 탄소섬유와 수지를 분리하여 탄소섬유를 재활용하였다. 에폭시의 분해도(Degree of decomposition)는 열중량분석기(TGA)와 시차 주사현미경(SEM)을 통해 확인하였다. 수지로부터 분리해낸 탄소섬유는 절단(Cutting)과 그라인딩(Grinding) 방법을 거쳐 탄소섬유 복합재료 시트(Sheet)를 제조하였다. 재활용 탄소 섬유로 제조된 탄소섬유 시트는 각각 다른 냉각조건에서 결정화 엔탈피(Crystallization enthalpy)와 기계적 특성, 표면과 단면의 형태를 분석하였다.