• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.67-70
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• 2000

In this paper, all SCR recombination currents including setback and graded layer's recombination currents are analytically introduced for the first time. Different emitter-base structures are tested to prove the validity of the model. In 1995, the analytical equations of electric field, electrostatic potential, and junction capacitance for abrupt and linearly graded heterojunctions with or without a setback layer was derived. But setback layer and linearly graded layer's recombination current was considered numerically. In this paper, recombination current model included setback layer and graded layer is proposed. New recombination current model also includes abrupt heterojunction's recombination current model. In this paper, new recombination current model analytically explains effects of setback layer and graded layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.330-335
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• 2003

This paper reports the optimum structure of the vacuum packaged Porous poly-silicon Nano-Structured (PNS) emitter. The PNS layer was obtained by electrochemical etching process into polycrystalline silicon layer in a process controlled to anodizing condition. Current-voltage studies were carried out to optimize process condition of electron emission properties as a function of anodizing condition and top electrode thickness. Also, we measured in advance the electron emission properties as a function of substrate temperature because the vacuum packaged process was performed under the condition of high temperature ambient (430$^{\circ}C$). Auger Electron Spectrometer (AES) studies shows that Au as a top-electrode was diffused to PNS layer during temperature experiments. Thus, we optimized the thickness of top-electrode in order to make the vacuum package PNS emitter. As a result, the vacuum Packaged PNS emitter was successfully emitted by optimizing process.

• Journal of the Korean Solar Energy Society
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• v.32 no.5
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• pp.102-107
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• 2012

Halogen lamp was applied to fabricate the selective emitter crystalline silicon solar cell. In selective emitter structure, the recombination of minority carriers is reduced with heavily doped emitter under metal grid, consequently improving the conversion efficiency. Laser selective emitter process which is recently used the most generally induces the damage on the silicon surface. However the lamp has enough heat to form heavily doped emitter layer by diffusing phosphorus from PSG without surface damage. In this work, we have studied to find the design and the suitable condition for halogen lamp such as power, time, temperature and figured out the possibility to fabricate the selective emitter silicon solar cell by lamp heating. The sheet resistance with $100{\Omega}/{\Box}$ was lower to $50{\Omega}/{\Box}$ after halogen lamp treatment. Heat transfer to lightly doped emitter region was blocked by using the shadow mask.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.2
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• pp.76-79
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• 1999

Low-hydrogenated DLC films were coated on the Mo-tip FEAs by 'layer-by-layer' process based on the plasma-enhanced CVD method. The hydrogen content in the DLC film deposited by the 'layer-by-layer' process was appeared to be remarkably lowered through SIMS analysis. Also, the low-hydrogenated DLC-coated Mo-tip FEA showed good potentiality for FED applications in terms of turn-on voltage, emission current, emission stability and light emitting uniformity.

• Korean Journal of Optics and Photonics
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• v.25 no.4
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• pp.193-199
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• 2014

The net effect of the emitter orientation, Mie scatters, and pillow lenses on the outcoupling efficiency (OCE) of a bottom-emitting OLED having an internal photonic crystal layer was investigated by a combined optical simulation based on the finite-difference time-domain method (FDTD) and the ray-tracing technique. The simulation showed that when the emitter orientation was horizontal with respect to the OLED surface, the OCE could be increased by 54% when a photonic crystal layer was employed, while it could be improved by 86% under optimized conditions of Mie scatters and pillow lenses applied to the glass substrate. The peculiar intensity distribution of the OLED, caused by the periodic lattice structure of the photonic crystal layer, could be ameliorated by inserting Mie scatters into the glass substrate. This study suggests that conventional outcoupling structures combined with control of the emitter orientation could improve the OCE substantially.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.347-350
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• 2001

A typical Mold method is to form a gate electrode, a gate oxide, and emitter tip after fabrication of mold shape using wet-etching of Si substrate. In this study, however, new Mold method using a side wall space structure is used in order to make sharper emitter tip with a gate electrode. Using LPCVD(low pressure chemical vapor deposition), a gate oxide and electrode layer are formed on a Si substrate, and then BPSG(Boro phospher silicate glass) thin film is deposited. After, the BPSG thin film is flowed into a mold as high temperature in order to form a sharp mold structure. Next TiN thin film is deposited as a emitter tip substance. The unfinished device with a glass substrate is bonded by anodic bonding techniques to transfer the emitters to a glass substrate, and Si substrate is etched using KOH-deionized water solution. Finally, we made sharp field emitter array with gate electrode on the glass substrate.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.405-408
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• 1998

Due to the large conduction band discontinuity between emitter base, OmGaAs HBT has an advantge to enable the hot electrons to inject into the base. In this paper, InAlGaAs/InGaAs HBT with the various emitter junction gradings and the modified collectors are simulated and analyzed by HMC(hybrid monte carlo) simulator in order to find a optimal structure for the shortest transit time. A minium base transit time (.tau.$_{b}$ ) of 0.21 ps was obtained for HBT with the grading layer, which is parabolically graded from x=1.0 to x=0.5. The minimum collector transit time (.tau.$_{c}$ ) of 0.31ps was found when the collector was modified by inserting p$^{[-10]}$ and p$^{+}$ layers. Thus HBT in combination with the emitter grading and the modified collector layer showed the cut-off frequency (f$_{T}$) of 183GHz.z.z.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.61-64
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• 2011

In order to grow the crystalline solar cells industry continuously, development of alternate low-cost manufacturing processes is required. Plasma doping system is the technique for introducing dopants into semiconductor wafers in CMOS devices. In photovoltaics, plasma doping system could be an interesting alternative to thermal furnace diffusion processes. In this paper, plasma doping system was applied for phosphorus doping in crystalline solar cells. The Plasma doping was carried out in 1~4 KV bias voltages for four minutes. For removing surface damage and formation of pn junction, annealing steps were carried out in the range of $800{\sim}900^{\circ}C$ with $O_2$ ambient using thermal furnace. The junction depth in about $0.35{\sim}0.6{\mu}m$ range have been achieved and the doping profiles were very similar to emitter by thermal diffusion. So, It could be confirmed that plasma doping technique can be used for emitter formation in crystalline solar cells.

• Korean Journal of Metals and Materials
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• v.49 no.11
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• pp.905-909
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• 2011

The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surfaces. One of the available front metal contacts is Ni/Cu plating, which can be mass produced via asimple and inexpensive process. A selective emitter, meanwhile, involves two different doping levels, with higher doping (${\leq}30{\Omega}/sq$) underneath the grid to achieve good ohmic contact and low doping between the grid in order to minimize the heavy doping effect in the emitter. This study describes the formation of a selective emitter and a nickel silicide seed layer for the front metallization of silicon cells. The contacts were thickened by a plated Ni/Cu two-step metallization process on front contacts. The experimental results showed that the Ni layer via SEM (Scanning Electron Microscopy) and EDX (Energy dispersive X-ray spectroscopy) analyses. Finally, a plated Ni/Cu contact solar cell displayed efficiency of 18.10% on a $2{\times}2cm^2$, Cz wafer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.575-579
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• 2010

The technologies of Ni/Cu plating contact is attributed to the reduced series resistance caused by a better contact conductivity of Ni with Si and the subsequent electroplating of Cu on Ni. The ability to pattern narrower grid lines for reduced light shading was combined with the lower resistance of a metal silicide contact and an improved conductivity of the plated deposit. This improves the FF (fill factor) as the series resistance is reduced. This is very much requried in the case of low concentrator solar cells in which the series resistance is one of the important and dominant parameter that affect the cell performance. A Selective emitter structure with highly dopeds regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing In this paper the formation of a selective emitter, and the nickel silicide seed layer at the front side metallization of silicon cells is considered. After generating the nickel seed layer the contacts were thickened by Cu LIP (light induced plating) and by the formation of a plated Ni/Cu two step metallization on front contacts. In fabricating a Ni/Cu plating metallization cell with a selective emitter structure it has been shown that the cell efficiency can be increased by at least 0.2%.