• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.61-70
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• 2007

The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

• The KIPS Transactions:PartA
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• v.16A no.4
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• pp.245-254
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• 2009

With the increasing adoption of embedded processors, the need of developing compilers for the embedded processors with timely manner is also growing. Retargeting has been adopted as a viable approach to constructing new compilers by modifying the back-end of an existing compiler. This paper proposes a test suite generation system for testing retargetable C compilers. The proposed system generates the test suite using the grammar coverage concept. Generally, the size of the test suite satisfying the grammar coverage of the source language is very large. Hence, the proposed system also provides the facility to reduce the size of the test suite. According to the experimental result, the reduced test suite can detect 75% of the compiler faults detected by the original test suite though the size of the reduced test suite is only 10% of that of the original test suite in average. This result indicates that the reduction technique proposed in this paper can be effectively used in the prior phase of the development procedure of the embedded compilers.

• The KIPS Transactions:PartD
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• v.15D no.4
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• pp.505-512
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• 2008

In order to do requirement-based testing of embedded system, we must have correct requirement specifications. But, natural language requirements of a client have ambiguity, inaccuracy, and inconsistency. To solve these problems, natural language requirements are modeled with modeling language such as UML and Simulink. During a modeling phase, the requirements are rearranged and retranslated in use-case. These activities are disadvantages of modeling. In this paper, we propose the technique, which is how to model a embedded system requirement into a model without rearranging and retranslating. This technique 1) represent a embedded system requirement with graphical language, and 2) model a requirement into a model. Because this technique only describes "what-to-do" of the requirement, this technique is useful to not only the low-level requirements but also the high-level requirements. We show some example systems modeled by REED, which has adopted this technique.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11
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• pp.3086-3096
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• 1999

To declare conformance of multi-protocol Implementation Under Test(IUT), every layer of the multi-protocol IUT should be tested. According to ISO9646, single-layer test method is applied to testing the highest layer of multi-protocol IUT and single-layer embedded test method is used for the layers by layer all the protocols in a multi-protocol IUT. This paper proposes a new method for testing a multi-protocol IUT. The proposed test method assumes that a multi-protocol IUT is under test and that the interfaces between the layers cannot be controlled or observed by the tester. We apply the proposed test method to TCP/IP and compare the application results with those of the existing test turns out that the proposed test method significantly reduces the number of test cases as well as the number of test events while providing the same test coverage. In addition, the proposed test method shows the capability to locate the layer that is source of failure in testing multi-protocol IUTs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.22-34
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• 1999

In this paper, an efficient test algorithm for embedded dual-port memories is presented. The proposed test algorithm can be used to test embedded dual-port memories faster than the conventional multi-port test algorithms and can be used to completely detect stuck-at faults, transition faults and coupling faults which are major target faults in embedded memories. Also, in this work, BIST which performs the proposed memory testing algorithm is designed using Verilog-HDL, and simulation and synthesis for BIST are performed using Cadence Verilog-XL and Synopsys Design-Analyzer. It has been shown that the proposed test algorithm has high efficiency through experiments on various size of embedded memories.

• Proceedings of the Korean Society For Composite Materials Conference
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• 2005.04a
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• pp.17-20
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• 2005

In-situ structural health monitoring of filament wound pressure tanks were conducted during water-pressurizing test using embedded fiber Bragg grating (FBG) sensors. We need to monitor inner strains during working in order to verify the health condition of pressure tanks more accurately because finite element analyses on filament wound pressure tanks usually show large differences between inner and outer strains. Fiber optic sensors, especially FBG sensors can be easily embedded into the composite structures contrary to conventional electric strain gages (ESGs). In addition, many FBG sensors can be multiplexed in single optical fiber using wavelength division multiplexing (WDM) techniques. We fabricated a standard testing and evaluation bottle (STEB) with embedded FBG sensors and performed a water-pressurizing test. In order to increase the survivability of embedded FBG sensors, we suggested a revised fabrication process for embedding FBG sensors into a filament wound pressure tank, which includes a new protecting technique of sensor heads, the grating parts. From the experimental results, it was demonstrated that FBG sensors can be successfully adapted to filament wound pressure tanks for their structural health monitoring by embedding.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.462-475
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• 2007

The Embedded system provides human-centric services in many fields of education, information, industry and service, and monitoring programs have been variously developed for managing, controlling and testing for these embedded systems. Currently, many kernel trace toolkits are being used for monitoring. These trace toolkits are so complicate that we present $ETT^{plus}$, our simple and explicit embedded kernel trace toolkit, for embedded systems and describe the transmission method for trace data between the embedded target system and the host system. $ETT^{plus}$ provides the solution to solve the problems such as the difficult kernel patch and file system dependency in existing kernel trace toolkits like LTT. Furthermore, we present the experimental results about embedded system performance evaluations such as system call execute time or network data transmission time by using $ETT^{plus}$.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.296-299
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• 2003

This paper presents the implementation of an integrated messaging gateway (IMG) based on the open services gateway initiative (OSGi) specification to deliver home messages between home and some telecommunication devices. The IMG has four service agents to support a diverse communication channel. In this paper, we describe a software architecture for a seamless messaging and device layouts in the IMG. And then, we detail each components allowing users to be notified automatically through a cellular phone, a telephone, and the Internet.

• Advanced Composite Materials
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• v.16 no.2
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• pp.115-134
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• 2007

This study proposes two new approaches for identifying damage patterns in a holed CFRP cross-ply laminate using an embedded fiber Bragg grating (FBG) sensor. It was experimentally confirmed that the reflection spectrum from the embedded FBG sensor was significantly deformed as the damage near the hole (i.e. splits, transverse cracks and delamination) extended. The damage patterns were predicted using forward analysis (a damage analysis and an optical analysis) with strain estimation and the proposed damage-identification method as well as the forward analysis only. Forward analysis with strain estimation provided the most accurate damage-pattern estimation and the highest computational efficiency. Furthermore, the proposed damage identification significantly reduced computation time with the equivalent accuracy compared to the conventional identification procedure, by using damage analysis as the initial estimation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.85-91
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• 1993

In this paper, we propose the test pattern generation algorithm of the embedded faulty MUX for the prevention of misdiagnosis of digital systems. When the system is partitioned with a large number of functional blocks, if the faults are exsisted in a embedded MUX then it can not diagnose the wanted observation of functional block. The proposed test pattern generstion algorithm can apply the MUXs that designd 2-level and multi-level both. Fault coverage becomes 100% and so it is no necessary of the additional fault simulation and the proposed algorithm that have the regulary and easily generated 2d test patterns. And we confirmed that the reduction of test cost becomes 85%, compared with the conventional segmentation testing scheme.