• Journal of Institute of Control, Robotics and Systems
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• v.22 no.12
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• pp.1034-1039
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• 2016

This paper presents the implementation and control of a small-scaled excavator system. The commercial miniature of an excavator system has been modified and its control hardware is embedded to access the feedback control. Encoder sensors are attached to the joint and a force sensor is mounted on the end-effector so that feedback position control is accessible as well as force control. The dynamic model of the excavator system is derived as a four linkage robot arm and its control performances are simulated. Experimental studies of contact force control tasks are conducted to test the control algorithm for the excavator system.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.10a
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• pp.537-540
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• 2018

본 논문은 Jetson_TX2(임베디드 보드)의 ROS(Robot Operating System)기반으로 맵 지도를 작성하고, SLAM 및 DQN(Deep Q-Network)을 이용한 목적지까지의 이동명령(목표 선속도, 목표 각속도)을 자이로센서로 측정한 현재 각속도를 이용하여 Cortex-M3의 기반의 MCU(Micro Controllor Unit)에 하달하여 엔코더(encoder) 모터에서 측정한 현재 선속도와 자이로센서에서 측정한 각속도 값을 이용하여 PID제어를 통한 실내 자율주행 서비스 로봇.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.119-124
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• 2009

In this paper, AMR-WB+ audio coder is implemented, in real-time, using Intel 400MHz Xscale PXA250 with 32bit RISC processor ARM9E-J(R)core. The assembly code for ARM9E-J(R)core is developed through the serial process of C code optimization, cross compile, assembly code manual optimization and adjusting the optimized code to Embedded Visual C++ platform. C code is trimmed on Visual C++ platform. Cross compile and assembly code manual optimization are performed on CodeWarrior with ARM compiler. Through these stages the code for both ARM EVM board and PDA is implemented. The average complexities of the code are 160.75MHz on encoder and 33.05MHz on decoder. In case of static link library(SLL), the required memories are 65.21Kbyte, 32.01Kbyte and 279.81Kbyte on encoder, decoder and common sources, respectively. The implemented coder is evaluated using 16 test vectors given by 3GPP to verify the bit-exactness of the coder.

• Journal of Broadcast Engineering
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• v.11 no.3 s.32
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• pp.320-325
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• 2006

An image is partitioned into non-overlapping $8{\times}8$ blocks fer JPEG compression. A scan order converter is placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. In general, its architecture requires two line memories for storing eight lines separately to allow the concurrent memory access by both the camera and JPEG processors. Although such architecture is simple to be implemented, it can be inefficient due to too excessive memory requirement as the image resolution increases. However, no deterministic addressing equation has been developed for scan conversion. In this paper, an effective memory addressing algorithm is proposed that can be devised only by adders and subtracters to implement a scan converter based on the single line memory.

• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.528-539
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• 2005

The H.264 has been adopted as the video codec for various multimedia services such as DMB and next-generation DVD because of its superior coding performance. However, the reference codec of the standard, the joint model (JM) contains quite a few algorithms which are too complex to be used for the resource-constraint embedded environment. This paper introduces very low-complexity H.264 encoding algorithm which is applicable for the embedded environment. The proposed algorithm was realized by restricting some coding tools on the basis that it should not cause too severe degradation of RD-performance and adding a few early termination and bypass conditions during the motion estimation and mode decision process. In case of encoding of 7.5fps QCIF sequence with 64kbpswith the proposed algorithm, the encoder yields worse PSNRs by 0.4 dB than the standard JM, but requires only $15\%$ of computational complexity and lowers the required memory and power consumption drastically. By porting the proposed H.264 codec into the PDA with Intel PXA255 Processor, we verified the feasibility of the H.264 based MMS(Multimedia Messaging Service) on PDA.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.736-745
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• 2002

In network delivery of compressed video, packets may be lost if the channel is unreliable like Internet. Such losses tend to of cur in burst like continuous bit-stream error. In this paper, we propose an effective error-concealment approach to which an error resilient video encoding approach is applied against burst errors and which reduces a complexity of error concealment at the decoder using data hiding. To improve the performance of error concealment, a temporal and spatial error resilient video encoding approach at encoder is developed to be robust against burst errors. For spatial area of error concealment, block shuffling scheme is introduced to isolate erroneous blocks caused by packet losses. For temporal area of error concealment, we embed parity bits in content data for motion vectors between intra frames or continuous inter frames and recovery loss packet with it at decoder after transmission While error concealment is performed on error blocks of video data at decoder, it is computationally costly to interpolate error video block using neighboring information. So, in this paper, a set of feature are extracted at the encoder and embedded imperceptibly into the original media. If some part of the media data is damaged during transmission, the embedded features can be extracted and used for recovery of lost data with bi-direction interpolation. The use of data hiding leads to reduced complexity at the decoder. Experimental results suggest that our approach can achieve a reasonable quality for packet loss up to 30% over a wide range of video materials.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.297-305
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• 2007

In the paper, a Motion JPEG2000 coder which has been set as the standard for image compression by the Digital Cinema Initiatives (DCI), an organization composed of major movie studios was implemented into a target FPGA. The DWT (Discrete Wavelet Transform) based on lifting and the Tier 1 of EBCOT (Embedded Block Coding with Optimized Truncation) which are major functional modules of the JPEG2000 were setup with dedicated hardware. The Tier 2 process was implemented in software. For digital cinema the tile-size was set to support $1024\times1024$ pixels. To ensure the real-time operations, three entropy encoders were used. When Verilog-HDL was used for hardware, resources of 32,470 LEs in Altera's Stratix EP1S80 were used, and the hardware worked stably at the frequency of 150Mhz.

• Journal of KIISE
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• v.45 no.1
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• pp.94-98
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• 2018

We propose Wide Inception ResNet (WIR Net) an optimized neural network architecture as a real-time semantic segmentation method for autonomous driving. The neural network architecture consists of an encoder that extracts features by applying a residual connection and inception module, and a decoder that increases the resolution by using transposed convolution and a low layer feature map. We also improved the performance by applying an ELU activation function and optimized the neural network by reducing the number of layers and increasing the number of filters. The performance evaluations used an NVIDIA Geforce GTX 1080 and TX1 boards to assess the class and category IoU for cityscapes data in the driving environment. The experimental results show that the accuracy of class IoU 53.4, category IoU 81.8 and the execution speed of $640{\times}360$, $720{\times}480$ resolution image processing 17.8fps and 13.0fps on TX1 board.

• The KIPS Transactions:PartB
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• v.12B no.7 s.103
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• pp.745-754
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• 2005

This paper proposes an information hiding algorithm using channel coding technique which can be used to detect transmission errors and to protect copyright for MPEG-2 video The watermark signal is generated by applying copyright information of video data to a convolutional encoder, and the signal is embedded into macro blocks in every frame while encoding to MPEG-2 video stream In the decoder, the embedded signal is detected from macro blocks in every frame, and the detected signal is used to localize transmission errors in the video stream. The detected signal can also be used to claim ownership of the video data by decoding it to the copyright Information. In this stage, errors in the detected watermark signal can be corrected by channel decoder. The 3 video sequences which consist of 300 frames each are applied to the proposed MPEG-2 codec. Experimental results show that the proposed method can detect transmission errors in the video stream while decoding and it can also reconstruct copyright information more correctly than the conventional method.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.4
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• pp.412-417
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• 2014

This paper presents the development and control of an omni-directional holonomic mobile robot platform, which is equipped with three lateral orthogonal-wheel assemblies. Omni-directionality can be achieved with decoupled rotational and translational motions. Simulation studies on collision avoidance are conducted. A real robot is built and its hardware is implemented to control the robot. Control algorithm is embedded on DSP and FPGA chips. Hardware for motor control such as PWM, encoder counter, serial communication modules is implemented on an FPGA chip. Experimental studies of following joystick commands are performed to demonstrate the functionality and controllability of the robot.