• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.8
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• pp.3076-3082
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• 2010

The techniques and the products which use various video compression codec are come out from army or civil field. In existing high-end PC environment, process of the video compression codec does not become a problem, but in embedded system environments which limited system resources, because the system load due to the high-resolution images compressed by high-density, issues of performance and utilization are highlighted. This paper proposes the DirectShow Filter interfaces which are a hardware method in order to solve the problem existing software algorithms for image compression performance and peripheral interfaces.

• Journal of Korea Multimedia Society
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• v.15 no.8
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• pp.1017-1030
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• 2012

Most watermarking schemes for video contents protection have been studied to increase watermark's robustness and invisibility against such compressions and many kinds of signal processing after embedding copyright information to the original contents. This paper proposes an active watermarking that infect watermark to contents in the video decoding process using embedded infectious watermark and control signals from a video encoder side. To achieve this algorithm, we design a kernel based watermarking in video encoder side that is possible to recover the original contents and watermark in watermark detection procedure perfectly. And then, by reversible de-watermarking in video decoder side, we design the active watermark infection method using detected watermark and control signal. This means that our system can provide secure re-distributions of video contents without any quality degration and watermark bit error against transcoding or re-encoding processing. By experimental results, we confirmed that the embedded watermark was infected by video contents and codec perfectly without any declines of compression ratio and video quality.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.97-100
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• 2007

In order to overcome many defects in the current JPEG standard of still image compression, the new JPEG2000 standard has been development. The JPEG2000 standard is based on the principles of DWT and EBCOT Entropy Coding. EBCOT(Embedded block coding with optimized truncation) is the most important technology in the latest image-coding standard, JPEG2000. However, EBCOT occupies the highest computation time to operate bit-level processing. Therefore, many researches have achieved methods to minimize computation speed of EBCOT. Thus, this paper proposes the method of context-extraction that improves computational architecture. This paper proposes efficient context coding method. The proposed algorithm would apply to hard-wired JPEG2000 Encoder that is used for compression of high resolution image.

• ETRI Journal
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• v.43 no.1
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• pp.109-119
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• 2021

Self-recovery is a tamper-detection and image recovery methods based on data hiding. It generates two types of data and embeds them into the original image: authentication data for tamper detection and reference data for image recovery. In this paper, a region-based scalable self-recovery (RSS) method is proposed for salient-object images. As the images consist of two main regions, the region of interest (ROI) and the region of non-interest (RONI), the proposed method is aimed at achieving higher reconstruction quality for the ROI. Moreover, tamper tolerability is improved by using scalable recovery. In the RSS method, separate reference data are generated for the ROI and RONI. Initially, two compressed bitstreams at different rates are generated using the embedded zero-block coding source encoder. Subsequently, each bitstream is divided into several parts, which are protected through various redundancy rates, using the Reed-Solomon channel encoder. The proposed method is tested on 10 000 salient-object images from the MSRA database. The results show that the RSS method, compared to related methods, improves reconstruction quality and tamper tolerability by approximately 30% and 15%, respectively.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.182-192
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• 2010

This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.917-923
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• 2011

In this paper, a new prediction based embedded compression (EC) codec algorithm for the JPEG2000 encoder system is proposed to reduce excessive memory requirements. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform (DWT) stages compared with direct implementation of the DWT engine of this paper. The LOCO-I predictor and MAP are widely used in many lossless picture compression codec. The proposed EC algorithm use these predictor which are very simple but surprisingly effective. The predictive EC scheme adopts a forward adaptive quantization and fixed length coding to encoding the prediction error. Simulation results show that our LOCO-I and MAP based EC codecs present only PSNR degradation of 0.48 and 0.26 dB in average, respectively. The proposed algorithm improves the average PSNR by 1.39 dB compared to the previous work in [9].

• The Journal of the Korea Contents Association
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• v.12 no.3
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• pp.77-83
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• 2012

In this paper, a low-complexity embedded compression (EC) Codec algorithm for the wavelet video coder is applied to reduce excessive external memory requirements. The EC algorithm is used to achieve a fixed compression ratio of 50 % under the near-lossless-compression constraint. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform stages compared with direct implementation of the wavelet video encoder of this paper. Furthermore, the EC scheme based on a forward adaptive quantization and fixed length coding can save bandwidth and size of buffer between DWT and SPIHT to 50 %. Simulation results show that our EC algorithm present only PSNR degradation of 0.179 and 0.162 dB in average when the target bit-rate of the video coder are 1 and 0.5 bpp, respectively.

• The KIPS Transactions:PartB
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• v.10B no.2
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• pp.189-196
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• 2003

This paper describes an error resilient video data transmission method using information hiding. In order to localize transmission errors in receiver, video encoder embeds one bit for a macro block during encoding process. Embedded information is detected during decoding process in the receiver, and the transmission errors can be localized by comparing the original embedding data. The localized transmission errors can be easily corrected, thus the degradation in a reconstructed image can be alleviated. Futhermore, the embedded information can be applied to protect intellectual property rights of the video data. Experimental results for 3 QCIF sized video sequenced composed of 150 frames respectively show that, while degradation in video streams in which the information is embedded is negligible, especially in a noisy channel, the average PSNR of reconstructed images can be improved about 5 dB by using embedded information. Also, intellectual property rights information can be effectively obtained from reconstructed images.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.