• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.88-94
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• 2011

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 ${\mu}A$ to 61 ${\mu}A$ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 $k{\Omega}$ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.115-122
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• 2014

In this paper, reliability is secured by sensing a post-program resistance of several tens of kilo ohms and restricting a read current flowing over an unblown eFuse within $100{\mu}A$ since RWL driver and BL pull-up load circuits using a regulated voltage of V2V ($=2V{\pm}10%$) are proposed to have a wide operating voltage range for eFuse OTP memory. Also, when a comparison of a cell array of 1 row ${\times}$ 32 columns with that of 4 rows ${\times}$ 8 columns is done, the layout size of 4 rows ${\times}$ 8 columns is smaller with $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$) than that of 1 row ${\times}$ 32 columns with $735.96{\mu}m{\times}61.605{\mu}m$ ($=0.04534mm^2$).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.509-518
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• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1205-1209
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• 1997

When the short fault current is flowed into a fuse, the notch of element is melted, and burnbacked by arc plasma, which caused by the voltage of fuse at both ends. The cutoff ability of fuse is heavily influenced by the degree of burnback. In this paper, we investigated the amount of burnback to the applied voltage di/dt variation, As a result, we confirmed that the amount of burnback is proportional to the variation of the applied voltage.

• Journal of Korean Society for Quality Management
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• v.40 no.3
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• pp.270-277
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• 2012

Purpose: In this paper, storage lifetime of delay system in the fuse of 81MM illuminating projectile is estimated. Methods: Accelerated degradation testings of tungsten delay system using both temperature and humidity stresses were performed, and then delay time increase of the systems were analyzed as degradation data based on distribution-based degradation processes. Results: The estimated storage lifetime of detonator is between 11.8 years and 17.6 years with each stress-life relationship. Conclusion: Comparing with field data, storage lifetime of 90% reliability is about 12 years.

• Proceedings of the Korea Society for Energy Engineering kosee Conference
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• 2007.11a
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• pp.320-325
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• 2007

• Journal of Astronomy and Space Sciences
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• v.21 no.4
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• pp.243-248
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• 2004

We present measurements of interstellar CO absorption lines in the spectra of 7 early-type stars that were observed with the FUSE(Far Ultraviolet Spectroscopic Explore.) Among 54 early-type target stars in the Galactic disk and halo observed with the BBFS(Berkeley Extreme and Far-ultraviolet Spectrometer), we choose 7 program stars (HD 37903, HD 97991, HD 149881, HD 156110, HD 164794, HD 214080 and HD 219188) which have only a single velocity component in the high-resolution optical measurements, in order to avoid line blending. To analyze the CO molecule, we select the E-X (0-0) band at $1076{\AA}$, which has a large oscillate. strength and is not blended with other interstellar absorption lines. We detect the CO absorption lines in three (HD 37903, HD 164794, and HD 214080) out of seven targets, and derive CO column densities for those targets. We also estimated the CO to $H_2$ ratios toward the three stars, based on the previously estimated $H_2$ column densities.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.84-87
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• 2010

We manufacture an antifuse OTP (One-time programmable) cell for analog trimming which will be used in power management ICs. For the antifuse cell using dual program voltage of VPP (=7V) and VNN (=-5V), the thin gate oxide is broken down by applying a voltage higher than the hard break-down voltage to the terminals of the antifuse. The area of the manufactured antifuse OTP cell using $0.18{\mu}m$ BCD process is $48.01{\mu}m^2$ and is about 44.6 percent of that of an eFuse cell. The post-program resistances of the antifuse are good with the values under several kilo ohms when we measure twenty test patterns.

• Journal of Microbiology and Biotechnology
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• v.15 no.1
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• pp.141-146
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• 2005

A new system for displaying proteins on the surface of Escherichia coli was developed using the Salmonella typhimurium outer membrane protein C (OmpC) as an anchoring motif. The C-terminal deletionfusion strategy was developed to fuse the polyhistidine peptides and green fluorescent protein (GFP) to the Cterminal of the truncated functional portion of OmpC. The polyhistidine peptides of up to 243 amino acids could besuccessfully displayed on the E. coli cell surface, which allowed recombinant E. coli to adsorb up to 34.2 μmol of Cd2+ per gram dry cell weight. The GFP could also be successfully displayed on the E. coli cell surface. These results suggest that the C-terminal deletion-fusion strategy employing the S. typhimurium OmpC as an anchoring motif provides a new efficient way for the display of large proteins on the surface of E. coli.