• Transactions on Electrical and Electronic Materials
• /
• v.1 no.4
• /
• pp.30-39
• /
• 2000

The variation of electrical properties of (Ba, Sr)TiO$_3$[BST] thin films deposited of RuO$_2$electrode with (Ba+Sr)/Tr ration was investigated. BST thin films with various (Ba+Sr)/Tr ration were deposited on RuO$_2$/Si substrates using in-situ RF magnetron sputtering. It was found that the electrical properties of BST films depends on the composition in the film. The dielectric constant of the BST films is about 190 at the (Ba+Sr)/Tr ration of 1.0, 1,025 and does not change markedly. But , the dielectric constant degraded to 145 as the (Ba+Sr)/Tr ratio increase to 1.0. In particular, the leakage current mechanism of the films shows the strong dependence on the (Ba+Sr)/Tr ration in the films. At the ration (Ba+Sr)/Tr=1,025, the Al/BST/RuO$_2$ capacitor show the most asymmetric behavior in the leakage current density, vs, electric field plot. It is considered that the leakage current of the (Ba+Sr)/Tr=1,025 thin films is controlled by the battier-Iimited process, i,e, Schottky emission.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.2
• /
• pp.335-344
• /
• 2014

In this paper we analysis for in out signal by previous study and implement virtual master that generate CGH processor signals. Also, we propose memory address mapping. By constructing the system model of our method and by analyzing the latencies according to the memory access methods in a system including our model and several other models, the low-latency memory access method has been obtained. The proposed method is reduce number of activation in DRAM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.11a
• /
• pp.71-74
• /
• 1996

Ta$_2$O$_{5}$ film ale recognized as promising capacitor dielectric for future DRAM\`s. The electrical properties of Ta$_2$O$_{5}$films greatly depend on the heating condition. In the practical fabrication process, several annealing process, such as the annealing of Al in H$_2$(about 40$0^{\circ}C$) and reflow of BPSG (borophosphosilicate glass) film in $N_2$(about 80$0^{\circ}C$), exist after deposition of Ta$_2$O$_{5}$ film. In this paper, we describe the temperature effect on the electrical properties of W/Ta$_2$O$_{5}$/Si structure. The thin film of Ta$_2$O$_{5}$ and tungsten have been deposited on p-si(100) wafer using the sputtering system. The heating temperature was varied from 500 to 90$0^{\circ}C$ in $N_2$for 30min and The degree of temperature is 100\`C. In a log(J/E$^2$) Vs 1/E plot of typical I-V data, we find a linear relationship for the temperature of 500, $600^{\circ}C$ and as deposition. This could indicate Fowler-Nordheim tunneling as the dominant mode of current transports. However, we can not find a linear relationship for the temperature above $700^{\circ}C$. This could not indicate Fowler-Nordheim tunneling as the dominant mode of current transport. The high frequency (1MHz) capacitance-voltage (C-V) of W/Ta$_2$O$_{5}$/Si Capacitor were investigated on the basis of shift in the threshold voltage and dielectric constant. The magnitude of the threshold voltage and dielectric constant depends on the heating temperature, and increases with heating temperature.temperature.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.7
• /
• pp.21-29
• /
• 2004

Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.1
• /
• pp.52-58
• /
• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.436-437
• /
• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.403-404
• /
• 2013

최근 scaling down의 한계에 부딪힌 DRAM과 Flash Memory를 대체하기 위한 차세대 메모리(Next Generation Memory)에 대한 연구가 활발히 진행되고 있다. ITRS (international technology roadmap for semiconductors)에 따르면 PRAM (phase change RAM), RRAM (resistive RAM), STT-MRAM (spin transfer torque magnetic RAM) 등이 차세대 메모리로써 부상하고 있다. 그 중 RRAM은 간단한 구조로 인한 고집적화, 빠른 program/erase 속도 (100~10 ns), 낮은 동작 전압 등의 장점을 갖고 있어 다른 차세대 메모리 중에서도 높은 평가를 받고 있다 [1]. 현재 RRAM은 주로 금속-산화물계(Metal-Oxide) 저항 변화 물질을 기반으로 연구가 활발하게 진행되고 있다. 하지만 근본적으로 공정 과정에서 산소에 의한 오염으로 인해 수율이 낮은 문제를 갖고 있으며, Endurance 및 Retention 등의 신뢰성이 떨어지는 단점이 있다. 따라서, 본 연구진은 산소 오염에 의한 신뢰성 문제를 근본적으로 해결할 수 있는 다양한 금속-질화물(Metal-Nitride) 기반의 저항 변화 물질을 제안해 연구를 진행하고 있으며, 우수한 열적 안정성($>450^{\circ}C$, 높은 종횡비, Cu 확산 방지 역할, 높은 공정 호환성 [2] 등의 장점을 가진 WN 박막을 저항 변화 물질로 사용하여 저항 변화 메모리를 구현하기 위한 연구를 진행하였다. WN 박막은 RF magnetron sputtering 방법을 사용하여 Ar/$N_2$ 가스를 20/30 sccm, 동작 압력 20 mTorr 조건에서 120 nm 의 두께로 증착하였고, E-beam Evaporation 방법을 통하여 Ti 상부 전극을 100 nm 증착하였다. I-V 실험결과, WN 기반의 RRAM은 양전압에서 SET 동작이 일어나며, 음전압에서 RESET 동작을 하는 bipolar 스위칭 특성을 보였으며, 읽기 전압 0.1 V에서 ~1 order의 저항비를 확보하였다. 신뢰성 분석 결과, $10^3$번의 Endurance 특성 및 $10^5$초의 긴 Retention time을 확보할 수 있었다. 또한, 고저항 상태에서는 Space-charge-limited Conduction, 저저항 상태에서는 Ohmic Conduction의 전도 특성을 보임에 따라 저항 변화 메카니즘이 filamentary conduction model로 확인되었다 [3]. 본 연구에서 개발한 WN 기반의 RRAM은 우수한 저항 변화 특성과 함께 높은 재료적 안정성, 그리고 기존 반도체 공정 호환성이 매우 높은 강점을 갖고 있어 핵심적인 차세대 메모리가 될 것으로 기대된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.7
• /
• pp.575-582
• /
• 2000

The Electrical conduction and optical properties of Ta$_{2}$/O$_{5}$ thin films as the insulators in DRAM capacitors were studied. Liquid Ta/sib 2//O sub 5/ were prepared by a sol-gel processing and multiple layers were applied by spin-coating up to thickness of 800$\AA$. At annealing temperature of 300~$600^{\circ}C$ the electrical conduction and specific dielectric constant were discussed the behaivor of carrier were observed by the Thermally Stimulated Current (TSC) at the temperature range of 30~23$0^{\circ}C$. At annealing temperature of 300~$600^{\circ}C$ the samples were found to be amorphous below $600^{\circ}C$ and crystalline over it. The electrical strength was about 2.2 MV/cm at 40$0^{\circ}C$. In spite of noncrystallization over 50$0^{\circ}C$ the increasing of leakage current due to pinholes and increasing creak. The refractive index was obtained maximum (2.2) at 40$0^{\circ}C$. The dielectric constant was obtained maximum(18.6) at 40$0^{\circ}C$. TSC was observed one peak at the temperature range of 30~23$0^{\circ}C$ from sample at 40$0^{\circ}C$. In the case of collecting voltage the peak size is decreased in proportion to collecting voltage and then the peak may be thought carrier to be a ionic space charge.e.

• Korean Journal of Materials Research
• /
• v.5 no.1
• /
• pp.42-54
• /
• 1995

$Ta_2O_5$ thin film IS a promising material for the high dielectrics of ULSI DRAM. In this study, $Ta_2O_5$ thin film was grown on p-type( 100) Si wafer by thermal metal organic chemical vapo deposition ( MCCVD) method and the effect of operating varialbles including substrate temperature( $T_s$), bubbler temperature( $T_ \sigma$), reactor pressure( P ) was investigated in detail. $Ta_2O_5$ thin film were analyzed by SEM, XRD, XPS, FT-IR, AES, TEM and AFM. In addition, the effect of various anneal methods was examined and compared. Anneal methods were furnace annealing( FA) and rapid thermal annealing( RTA) in $N_{2}$ or $O_{2}$ ambients. Growth rate was evidently classified into two different regimes. : (1) surface reaction rate-limited reglme in the range of $T_s$=300 ~ $400 ^{\circ}C$ and (2: mass transport-limited regime in the range of $T_s$=400 ~ $450^{\circ}C$.It was found that the effective activation energies were 18.46kcal/mol and 1.9kcal/mol, respectively. As the bubbler temperature increases, the growth rate became maximum at $T_ \sigma$=$140^{\circ}C$. With increasing pressure, the growth rate became maximum at P=3torr but the refractive index which is close to the bulk value of 2.1 was obtained in the range of 0.1 ~ 1 torr. Good step coverage of 85. 71% was obtained at $T_s$=$400 ^{\circ}C$ and sticking coefficient was 0.06 by comparison with Monte Carlo simulation result. From the results of AES, FT-IR and E M , the degree of SiO, formation at the interface between Si and TazO, was larger in the order of FA-$O_{2}$ > RTA-$O_{2}$, FA-$N_{2}$ > RTA-$N_{2}$. However, the $N_{2}$ ambient annealing resulted in more severe Weficiency in the $Ta_2O_5$ thin film than the TEX>$O_{2}$ ambient.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.363-363
• /
• 2014

Ruthenium (Ru) has attractive material properties due to its promising characteristics such as a low resistivity ($7.1{\mu}{\Omega}{\cdot}cm$ in the bulk), a high work function of 4.7 eV, and feasibility for the dry etch process. These properties make Ru films appropriate for various applications in the state-of-art semiconductor device technologies. Thus, it has been widely investigated as an electrode for capacitor in the dynamic random access memory (DRAM), a metal gate for metal-oxide semiconductor field effect transistor (MOSFET), and a seed layer for Cu metallization. Due to the continuous shrinkage of microelectronic devices, better deposition processes for Ru thin films are critically required with excellent step coverages in high aspect ratio (AR) structures. In these respects, atomic layer deposition (ALD) is a viable solution for preparing Ru thin films because it enables atomic-scale control of the film thickness with excellent conformality. A recent investigation reported that the nucleation of ALD-Ru film was enhanced considerably by using a zero-valent metallorganic precursor, compared to the utilization of precursors with higher metal valences. In this study, we will present our research results on the synthesis and characterization of novel ruthenium complexes. The ruthenium compounds were easy synthesized by the reaction of ruthenium halide with appropriate organic ligands in protic solvent, and characterized by NMR, elemental analysis and thermogravimetric analysis. The molecular structures of the complexes were studied by single crystal diffraction. ALD of Ru film was demonstrated using the new Ru metallorganic precursor and O2 as the Ru source and reactant, respectively, at the deposition temperatures of $300-350^{\circ}C$. Self-limited reaction behavior was observed as increasing Ru precursor and O2 pulse time, suggesting that newly developed Ru precursor is applicable for ALD process. Detailed discussions on the chemical and structural properties of Ru thin films as well as its growth behavior using new Ru precursor will be also presented.