• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.263-266
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• 2000

In this paper we develop a dual storage device to store a lot of data safely and reliably in communication system. The device consists of micro-controller, FPGA and hard disk. It provides many functions those are rebuilding, automatic remapping, host service and remote host service. The developed device can be used instead of expensive storage device like flash memory in various communication systems.

• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.1
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• pp.106-115
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• 1994

A parallel integration approach is proposed for real-time simulation of controlled mechanical systems. The proposed approach, which employs the dual-rate integration method in a parallel computing environment, is developed to deal with stiffness and high frequency characteristics of the controlled mechanical systems effectively. Numerical experiments are performed to demonstrate the effectiveness of the approach in shared memory multiprocessors, Alliant FX/8 and Alliant FX/80.

• Proceedings of the Acoustical Society of Korea Conference
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• 1995.06a
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• pp.137-140
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• 1995

In the paper, CDMA's vocoder algorithm, QCELP, was analyzed. And, 16-bit programmable DSP core for QCELP was designed. When it is used two MACs in DSP, we can implement low-power DSP and estimate decrease of parameter computation speed. Also, we implemented in FIFO memory using register file to increase the access time of the data. This DSP was designed using logic synthesis tool, COMPASS, by top-down design methodology. Therefore, it is possible to cope with rapid change at mobile communication market.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1638-1642
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• 2003

In this paper, we have analyzed the power spectra and evaluate the performance of DTMF receiver by using the quick Fourier transform(QFT) algorithm. The economical signals detection of dual-tone multifrequency(DTMF) receiver is an important factor when developing cost-effective telecommunication equipment. In experimental results, it shows that reducing memory waste and can process the real-time.

• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.600-603
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• 2009

The liquid crystal device with switchable dynamic mode and memory mode has been investigated and developed. The proposed device reveals splay, ${\pi}$ twist and bend states by selective switching among them. In the dynamic mode, this device is operated in the bend state which exhibits the wide view angle and fast response time properties due to the self-compensated bend structure and flow accelerated fast response time. In the memory mode, the permanent memory characteristics in the splay and ${\pi}$ twist sates are obtained, respectively. The switching mechanisms of the tristate device are also proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.20-33
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• 2002

As dual port RAMs are widely used in the various applications, the need for an efficient algorithm to diagnose faults in dual port RAMs is increased. In this paper we propose an efficient algorithm that can diagnose all kinds of faults in dual port RAMs. In addition, the new algorithm can distinguish various fault models and locate the position related to each fault. Using the new algorithm, fault diagnosis for dual port RAMs can be performed efficiently and the performance evaluation with previous approaches proves the efficiency of the new algorithm.

• Journal of Convergence for Information Technology
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• v.10 no.12
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• pp.216-225
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• 2020

This study was conducted to qualitatively analyze the selected research through a systematic review to find out application method, outcome measures, and intervention effects of dual task. We searched for published studies from January 2010 to December 2019. Electrical database were PubMed and ProQuest. Search terms were 'dual task' OR 'multi modal' AND 'mild cognitive impairment' OR 'dementia' OR 'Alzheimer's disease'AND 'intervention' OR 'rehabilitation. There were 8 studies selected finally. The dual task was applied not as a single intervention but as a combined intervention with other exercises. The contents of dual task were consisted of motor and cognitive tasks to be independent each other. The outcome measures included general cognitive function such as MMSE and CERAD, executive function, and memory. Additionally the dual task cost was also used to identify the direct improvement of the dual task. This study could provide informations of dual task application on elderly with cognitive impairment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1455-1462
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• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.4
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• pp.1-9
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• 2012

LCD(Liquid Crystal Display) commonly used as an output device has a drawback of slow response time compared with CRT display. This drawback causes motion blur especially when an abrupt intensity change occurs in an image sequence as time goes on. To overcome the problem of slow response time overdriving technique has been used in TCON of LCD. In this technique, the previous frame data has to be compressed and stored in an external memory. Considering both chip size of TCON and computational complexity, AM-BTC has been applied to the 8bit HD display driver. However, the conventional method is not suitable for 10 bit Full HD because 10 bit Full HD data is much larger than that of 8 bit HD data. Being applied to 10 bit Full HD display driver, the conventional method increase cost by enlarging the external memory size of TCON or deteriorates image quality. In this paper, we propose dual BTC image coding technique for Full HD display driver that is an adaptive coding scheme according to morphological information of each sample block. Through experiments, it is verified that the proposed Dual BTC method performs better than the conventional method not only quantitatively but also qualitatively.