• Phonetics and Speech Sciences
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• v.6 no.4
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• pp.47-52
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• 2014

This study investigated how the degree of attention modulates English learners' perception of Korean stop contrasts. The contributions of VOT and F0 in perceiving Korean stops were examined while availability of attentional resources was manipulated using a dual-task paradigm. Results demonstrated the attentional modulation in the use of VOT, but not in F0: under less attention, the contribution of VOT to the perception of aspirated stops decreased, whereas that of lenis stops increased, which suggests more native-like performance. This implies that the role of attention in perceiving non-native contrasts might differ depending on how equivalent the acoustic and perceptual cues are between L1 and target L2 contrasts.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.227-233
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• 2006

In order to reduce blocking artifacts and improve compression efficiency, H.264/AVC standard employs an adaptive in-loop deblocking filter. This paper proposes a new hardware architecture of the deblocking filter that employs a four-stage pipelined structure with an efficient data distribution. The proposed architecture allows a simultaneous supply of eight data samples to fully utilize the pipelined filter in both horizontal and vertical filterings. This paper also presents a new filtering order and data reuse scheme between consecutive macroblock filterings to reduce the communication for external memory access. The number of required cycles for filtering one macroblock (MB) is 357 cycles when the proposed filter uses dual port SRAMs. This execution speed is only 41.3% of that of the fastest previous work.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1403-1410
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• 1997

Because streaming mode connection server suitable to wide area ATM networks performs transmission, reception and lookup with time restriction for the transmission time of a cell, it has demerits of large cell loss incase that burst traffic occurs. Therefore, in this paper to decrease cell loss we propose a high speed CAM (Content Addressable Memory) which is capable of processing data of streaming mode connections server at a high speed. the proposed CAM is applied to forwarding table VPC map which performs function to output connection numbers about input VPI(Virtual Path Identifier)/VCI(Virtual Channel Identifier). The designed high speed CAM consist of DBL(Dual Bit Line) CAM structure performed independently write operation and match operation and two-port SRAM structure. Also, its simulation verification and full-custom layout is performed by Hspice and Composs tools in 0.8 .$\mu$m design rule.

• 전기의세계
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• v.36 no.3
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• pp.190-204
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• 1987

본고에서는 이중입출력 메모리(Dual-Port RAM)를 이용한 영상 입력장치(Image Memory)의 설계 및 그 제어 신호 발생기에 대하여 논하였다. 이중 입출력 메모리 소자인 TMS4161은 기존의 표준 64K x 1DRAM Port와 256bit의 내부적 Shift REgister와 연결된 Serial Port가 있어서, 실시간 영상 처리 및 그래픽 용으로 사용하기에 적합하나, 그 사용에 있어서 가장 어려운 문제로 제안된 주소 신호 발생기 및 요구중재기에 대한 해결 방안을 제시하였다. 또한 서로 독립적인 두개의 입출력 장치가 있다는 장점을 이용하여 하드웨어에 의한 실시간 처리도 가능한 구조로 쉽게 확장할 수 있어서 소프트웨어에 의한 실시간 처리로 가능하리라 사료된다. 앞으로는 512x512x8의 영상 메모리 구조 뿐만 아니라 1024x1024x8의 영상메모리 구조에 대하여 더욱 연구할 필요가 있다고 본다.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.105-108
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• 2000

The economical detection of dual-tone multifrequency(DTMF) signals is an important factor when developing cost-effective telecommunication equipment. Each channel has independently a DTMF receiver, and I t informs the detected signal to processors. This paper analyze the power spectra and evaluate the performance of DTMF receiver by using tile quick Fourier transform(QFT) algorithm. As experimental results, it show the improved performance to the DTMF receivers and reduce memory waste and process the real-time.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.631-632
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• 2006

In this paper, acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2476-2479
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• 1998

The masticatory muscle relaxation appliance is developed to improve the malhabit of tooth clenching of the wearer. The repeated clenching of the tooth causes excessive attrition of tooth set. The intraoral appliance measures the tooth clenching pressure data and transmits the data to masticatory muscle relaxation appliance. The appliance compares the pressure data with the reference value and generates the warning signal. The relaxation appliance also stores the clenching pressure data for clenching habit analysis. The appliance is designed with a microprocessor, real time clock, nonvolatile read write memory and dual serial communication ports.

• BMB Reports
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• v.42 no.8
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• pp.475-481
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• 2009

Emerging data demonstrate pivotal roles for brain insulin resistance and insulin deficiency as mediators of cognitive impairment and neurodegeneration, particularly Alzheimer's disease (AD). Insulin and insulin-like growth factors (IGFs) regulate neuronal survival, energy metabolism, and plasticity, which are required for learning and memory. Hence, endogenous brain-specific impairments in insulin and IGF signaling account for the majority of AD-associated abnormalities. However, a second major mechanism of cognitive impairment has been linked to obesity and Type 2 diabetes (T2DM). Human and experimental animal studies revealed that neurodegeneration associated with peripheral insulin resistance is likely effectuated via a liver-brain axis whereby toxic lipids, including ceramides, cross the blood brain barrier and cause brain insulin resistance, oxidative stress, neuro-inflammation, and cell death. In essence, there are dual mechanisms of brain insulin resistance leading to AD-type neurodegeneration: one mediated by endogenous, CNS factors; and the other, peripheral insulin resistance with excess cytotoxic ceramide production.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.9
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• pp.1162-1170
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• 1995

In this paper, we present a message transfer scheme for efficient message passing in the hierarchically structured multiprocessor computer SPAX(Scalable Parallel Architecture computer based on X-bar network). The message transfer scheme provides interface not only with operating system but also with end users. In order to transfer two types of control message and data message efficiently, it supports both of memory-mapped transfer and DMA-based transfer. Dual-port RAMs are used as message buffers, and control and status registers provide efficient programming interface. Interlaced parity scheme is adopted for error control. If any error is detected at receiving node, errored packet is resent by sender according to retry mechanism. In conjunction with retry mechanism, watchdog timers are used to protect infinite waiting and repeated retry. The proposed message transfer scheme can be applied to input/output nodes and communication connection nodes as well as processing nodes in the SPAX.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.