• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• 수산해양교육연구
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• 제25권4호
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• pp.998-1007
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• 2013

At container terminals, a major measurement of productivity can be work efficiency. For improving the productivity of container crane, the more efficient container yard operation method is necessary in container terminals. Recently, container terminal operators make an experiment on the dual cycle operation, which ship loading/unloading were carried out simultaneously, for increasing the productivity of container crane. In this paper, propose a system operating efficient dual cycle methods as utilize Ad-hoc technology in distributed port operation system. The dual cycle methods that proposed recognizes position information of Y/T during an action in Ad-hoc networks in case of container transfer works by real time as load an Ad-hoc module to Y/T taking charge of a container transfer with quay and yard. Utilize Ad-hoc networks technology in an operating system of container yard, and efficiently distributed processing done Y/T to container crane compare with operation systems of the existing dedicated method, and an improvement can do an operating system of an yard.

• 한국항해항만학회지
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• 제35권1호
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• pp.71-76
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• 2011

최근 컨테이너 터미널의 관리자들은 안벽의 생산성을 높이기 위해서 양 적하를 동시에 할 수 있는 더블 사이클이나 듀얼 사이클을 시도하고 있다. 하지만 실제 터미널의 데이터를 이용하여 듀얼 사이클을 발생시켰을 경우 YT(Yard Tractor) 배정 방법이나, QC(Quay Crane)의 작업의 속도, 야드의 수출컨테이너 위치 등에 따라 효율성이 저하될 수 있다. 특히 기존의 야드 운영방식으로는 듀얼 사이클이나 더블 사이클을 효율적으로 지원하기 어렵다. 따라서 본 논문에서는 실제 터미널에서 듀얼 사이클을 사용할 때 효율성을 더 높일 수 있는 터미널야드 운영방법을 제시한다. 모형은 시뮬레이션 분석 소프트웨어인 Arena를 이용하여 수립되었다.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2011년도 추계학술대회
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• pp.170-171
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• 2011

전체 수 출입 공급망 사슬관리에 있어서 항만의 운영 효율성은 아주 중요하다. 컨테이너 터미널에서는 안벽작업의 효율성을 극대화하기 위하여 더블 사이클과 듀얼 사이클 방법이 소개되었고, 야드 트랙터 할당의 효율성을 높이기 위해서 야드 트랙터(YT) 풀링 방법이 제시되었다. 모형은 시뮬레이션 분석 소프트웨어인 Arena를 이용하여 수립되었다.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2010년도 추계학술대회
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• pp.110-111
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• 2010

최근 컨테이너 터미널의 관리자들은 안벽의 생산성을 높이기 위해서 양 적하를 동시에 할 수 있는 더블 사이클이나 듀얼 사이클을 시도하고 있다. 하지만 실제 터미널의 데이터를 이용하여 듀얼 사이클을 발생시켰을 경우 YT(Yard Tractor) 배정 방법이나, QC(Quay Crane)의 작업의 속도, 야드의 수출컨테이너 위치 등에 따라 효율성이 저하 될 수 있다. 따라서 본 논문에서는 실제 터미널에서 듀얼 사이클을 사용할 때 효율성을 더 높일 수 있는 터미널 운영방법을 제시한다.

• Journal of Power Electronics
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• 제14권6호
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• pp.1217-1223
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• 2014

A novel half load-cycle worked dual input single output (DISO) DC/AC inverter is presented. The basic circuit consists of a dual buck regulator, which works in continuous current mode. The working principle of DISO DC/AC inverter has been used. The control method applied for half load-cycle worked DISO DC/AC inverter has been studied. The control effects of the open-loop proportional control and closed-loop proportional-integral control are compared by using PSIM software. The parameters are adopted in the realistic simulation and experiment test. Moreover, the waveforms, such as voltage of modulation reference signal and output voltage, were given. The simulation and experiment results proved that the half load-cycle worked DISO DC/AC inverter could achieve good performance, gain a line frequency of 50 Hz, and verify the correctness of theoretical analysis.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권11호
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• pp.3780-3797
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• 2022

The estimation of radio map (RM) is a fundamental and critical task for the network planning and optimization performance of mobile communication. In this paper, a RM estimation method is proposed based on a deep dual learning structure. This method can simultaneously and accurately reconstruct the urban building map (UBM) and estimate the RM of the whole cell by only part of the measured reference signal receiving power (RSRP). Our proposed method implements UBM reconstruction task and RM estimation task by constructing a dual U-Net-based structure, which is named RadioCycle. RadioCycle jointly trains two symmetric generators of the dual structure. Further, to solve the problem of interference negative transfer in generators trained jointly for two different tasks, RadioCycle introduces a dynamic weighted averaging method to dynamically balance the learning rate of these two generators in the joint training. Eventually, the experiments demonstrate that on the UBM reconstruction task, RadioCycle achieves an F1 score of 0.950, and on the RM estimation task, RadioCycle achieves a root mean square error of 0.069. Therefore, RadioCycle can estimate both the RM and the UBM in a cell with measured RSRP for only 20% of the whole cell.

• Journal of Power Electronics
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• 제7권2호
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• pp.118-123
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• 2007

This paper presents a new ZCS-PWM high frequency inverter. Zero current switching operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. Dual duty cycle control scheme is used to provide a wide range of high frequency AC output power regulation that is important in many high frequency inverter applications. It found that a complete soft switching operation can be achieved even for low power setting ranges by introducing high-frequency dual duty cycle control scheme. The proposed high frequency inverter is more suitable for consumer induction heating(IH) applications. The operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.129-131
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• 2006

This paper presents a new ZVS-PWM high frequency inverter. The ZVS operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. The operating principle and the operating characteristics of the new high frequency circuit treated here are illustrated and evaluated on the basis of simulation results. It was examined that the complete soft switching operation can be achieved even for low power setting ranges by introducing the high frequency dual duty cycle control scheme. In the proposed high frequency inverter treated here, the dual mode pulse modulation control strategy of the asymmetrical PWM in the higher power setting ranges and the lower power setting ones, the output power of this high frequency inverter could introduce in order to extend soft switching operation ranges. Dual duty cycle is used to provide a wide range of output power regulation that is important in many high frequency inverter applications. It is more suitable for induction heating applications the operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

• Journal of Power Electronics
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• 제19권2호
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• pp.454-462
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• 2019

When compared to traditional bridge-type inverters, the dual-buck inverter has a higher reliability due to the fact that its bridge legs do not have a shoot-through problem. In this paper, the working principle of the dual-buck inverter is analyzed. A comparison of the working modes under full-cycle and half-cycle control is discussed. With half-cycle control, the inverter can realize a higher efficiency. However, this results in current zero-crossing distortion. The corresponding control strategy of the dual-buck inverter is proposed in order to realize both high efficiency and low current harmonic distortion. In addition, the system stability is analyzed. Dead-time is unnecessary due to the advantages of the topology. Thus, the current harmonic distortion can be further reduced. An inverter with the proposed control strategy has the advantages of high reliability, high efficiency and low current harmonic distortion. Finally, simulation and experimental results are given to verify the theoretical analysis.