• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Journal of Aerospace System Engineering
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• v.14 no.6
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• pp.79-84
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• 2020

Cooler driver electronics (CDE) for maintaining low temperature of the satellite payload IR sensor consists of a compressor that has a pulsation current load condition when it is operated. This pulsation current produces large voltage fluctuation, which affects both load and regulated bus stability. Thus, CDE power conditioning system consists of a primary bus, infrared power distribution unit for battery charging and protection, reverse current protection diode, and battery, which is used as a buffer. In this study, the operational mode analysis is performed by each part with equivalent impedance modeling verified through system level simulation. From this mode analysis, the safety margin for state of charge and open circuit voltage of the battery is determined for satisfying the minimum operational voltage of the CDE load.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.378-385
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• 2007

AC PDP has disadvantages that power consumption and sustain voltage are high. An energy recovery circuit for AC PDPs with reduced sustain voltage was proposed to solve these disadvantages. However, the circuit has disadvantage that the switching elements are performed hard switching at the start point of discharge and sustaining region. The reason is that the panel voltage is lower than sustain voltage at that point. In this paper, we propose the improved driving method that switching devices are operated with ZVS by using CIM(Current Infection Method) also at that point. CIM region is designed by theoretical circuit analysis. Finally, the validity of the proposed driving method is verified by the simulations and experimentation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.67-74
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• 2004

As data rate was increased, the conventional burst-mode automatic power control circuit caused errors due to the effort of the mark density variation. To solve this problem we invented a new structured peak-comparator which could eliminate the effect of the mark density variation even in high date rate, and revised the conventional one using it. We proposed a burst-mode automatic power control circuit robust to mark density variations. We found that the peak-comparator in the proposed automatic power control circuit was very robust to mark density variations because it affected very little by the mark density variation in high date rate and in the wide variation range of the reference current and the difference current.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.707-710
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• 2002

A 120kV/70A high voltage switch has been installed at Korea Atomic Energy Research Institute in Taejon to supply power with Korea Superconducting Tokamak Advanced Research (KSTAR) Neutral Beam Injection (NBI) system. NBI system requires fast cutoff of the power supply voltage for protection of the grid when arc detected and fast turn-on the voltage for sustaining the beam current. Therefore the high voltage switch and arc current detection circuit are important part of the NBI power supply and there are much need for high voltage solid state switches in NBI system and a broad area of applications. This switch consisted of 100 series connected MOSFETs and adopted the proposed simple and reliable gate drive circuit without bias supply, Various results taken during the commissioning phase with a 100kW resistive load and NBI source are shown. This paper presents the detailed design of 120kV/70A high voltage MOSFETs switch and simple gate drive circuit. Problems with the high voltage switch and gate driver and solutions are also presented.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.586-592
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• 2018

In this paper, HIC with various functions is proposed for the design 140W LED power control circuit. The proposed HIC integrates constant voltage/constant current circuit, short circuit protection circuit, internal constant voltage circuit, and dimmer circuit, thereby reducing the horizontal length of the PCB by 16% comparing with the conventional system. Through various experiments, we verified the performance of each block implemented inside of HIC with numerical results. (Constant voltage variation ratio: 2.9%, dimmer circuit duty variation within 5%, stable short protection at 720 mA) Since the PCB area can be significantly reduced by applying the proposed HIC. It is possible to reduce the PCB manufacturing time which takes up most of the manufacturing time, however, It is expected that the faulted power module can be replaced without replacing the whole PCB, so that maintenance / repair can be made easier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.834-843
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• 2016

In this paper, the design of a PIN diode S-band transfer-type SP4T including its driver circuit is presented. Each path of the SP4T is composed of the cascade connection of series-shunt PIN diodes to improve the isolation performance. The SP4T is implemented using chip type PIN diodes and a 20 mil AIN substrate fabricated using thin film technology. The driver circuit for the SP4T is designed using a multiplexer and four NMOS-PMOS push-pull pair. From on-wafer measurement, the fabriacted SP4T shows a maximum insertion loss of 1.1 dB and a minimum isolation of 41 dB. The time performance of the driver circuit is evaluated using the packaged PIN diodes with the identical PIN diode chip, and the transition time for on-off and off-on are below 100 nsec. For an input power level of 150 W, the measured insertion loss and isolation are close to those of the on-wafer measurement taking into consideration of the coaxial package mismatch and insertion loss.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.2
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• pp.107-115
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• 2015

In this paper, a small-area 32-bit differential paired eFuse OTP memory for power ICs is designed. In case of smaller number of rows than that of columns for the OTP memory cell array, a scheme for the cell array reducing the number of SL driver circuits requiring their larger layout areas by routing the SL (source line) lines supplying programming currents for eFuse links in the row direction instead of the column direction as well as a core circuit is proposed. In addition, to solve a failure of being blown for non-blown eFuse links by the electro-migration phenomenon, a regulated voltage of V2V ($=2V{\pm}0.2V$) is used to a RWL (read word line) driver circuit and a BL (bit line) pull-up driver circuit. The layout size of the designed 32-bit eFuse OTP memory is $228.525{\mu}m{\times}105.435{\mu}m$, which is confirmed to be 20.7% smaller than that of the counterpart using the conventional cell array routing, namely $197.485{\mu}m{\times}153.715{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.83-91
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• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.