• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1174-1177
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• 2006

A bottom contact organic thin film transistor (OTFT) is fabricated with an organic double-layered gate insulator (GI) and pentacene. The PMMA and MNB layers are treated on gate insulator and source/drain (S/D, Au) before depositing pentacene to investigate device properties and pentacene growth. The sequence of surface treatment affects a device performance seriously. The ultra-thin PMMA (below 50A) was deposited on organic gate insulator and S/D metal by spin coating method, which showed no deterioration of on-state current (Ion) although bottom contact structure was exploited. We proposed that the reason of no contact resistance (Rc) increase may be due to a wettability difference in between PMMA / Au and PMMA / organic GI. As a result, the device treated by $PMMA\;{\rightarrow}\;MNB$ showed much better Ion behavior than those fabricated by $MNB\;{\rightarrow}\;PMMA$. We will report the important physical and electrical performance difference associated with surface treatment sequence.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.186-189
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and room temperature process. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing process. The OTFT array with dielectric layer and organic active semiconductor layer formed at room temperature or at a temperature lower than $40^{\circ}C$. The microcontact printing process using SAM and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even submicron size, and reduced the fabrication process by 10 steps compared with photolithography. Since the process was done in room temperature, there was no pattern shrinkage, transformation, and bending problem appeared. Also, it was possible to improve electric field mobility, to decrease contact resistance, to increase close packing of molecules by SAM, and to reduce threshold voltage by using a big dielectric.

• ETRI Journal
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• 제39권2호
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• pp.292-299
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• 2017

We propose pulse-mode dynamic $R_on$ measurement as a method for analyzing the effect of stress on large-scale high-power AlGaN/GaN HFETs. The measurements were carried out under the soft-switching condition (zero-voltage switching) and aimed to minimize the self-heating problem that exists with the conventional hard-switching measurement. The dynamic $R_on$ of the fabricated AlGaN/GaN MIS-HFETs was measured under different stabilization time conditions. To do so, the drain-gate bias is set to zero after applying the off-state stress. As the stabilization time increased from $ 0.1{\mu}s$ to 100 ms, the dynamic $R_on$ decreased from $160\Omega$ to $2\Omega$. This method will be useful in developing high-performance GaN power FETs suitable for use in high-efficiency converter/inverter topology design.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.312-317
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• 2015

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

• 산업기술연구
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• 제26권A호
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• pp.101-108
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• 2006

This study is the results of experimental and numerical study on the consolidational behavior of multi-layered soft soil ground installed with plastic board drains (PBD). Centrifuge model tests with a marine clay sampled from field were performed to investigate the consolidational behavior of multi-layered ground where a dredged soil was placed on the soft clay ground and PBDs were installed. Test results were compared with those of numerical analyses, using the 2-D equivalent model previously proposed. From test results, it was found that the amount of consolidation settlement occurred in the original ground due to embankment surcharge loads was in the range of 38% of total settlement in the whole ground. From the results of cone penetration tests executed after finishing the centrifuge model tests, the cone resistance was found to increase with depth. The measured water contents inbetween PBDs were in the ranges of 38~50% and their values tended to increase with increasing the distance between PBDs.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.276-276
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• 2014

High-performance, fully-transparent, and top-gated oxide thin-film transistor (TFT) was successfully fabricated with Ta2O5 high-k gate dielectric on a glass substrate. Through a self-passivation with the gate dielectric and top electrode, the top-gated oxide TFT was not affected from H2O and O2 causing the electrical instability. Heat-treated InSnO (ITO) was used as the top and source/drain electrode with a low resistance and a transparent property in visible region. A InGaZnO (IGZO) thin-film was used as a active channel with a broad optical bandgap of 3.72 eV and transparent property. In addition, using a X-ray diffraction, amorphous phase of IGZO thin-film was observed until it was heat-treated at 500 oC. The fabricated device was demonstrated that an applied electric field efficiently controlled electron transfer in the IGZO active channel using the Ta2O5 gate dielectric. With the transparent ITO electrodes and IGZO active channel, the fabricated oxide TFT on a glass substrate showed optical transparency and high carrier mobility. These results expected that the top-gated oxide TFT with the high-k gate dielectric accelerates the realization of presence of fully-transparent electronics.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.595-596
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and low-temperature processes. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing which is high-resolution lithography technology using polydimethylsiloxane(PDMS) stamp. The OTFT array with dielectric layer and organic active semiconductor layers formed at room temperature or at a temperature tower than $40^{\circ}C$. The microcontact printing process using SAM(self-assembled monolayer) and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even nano size, and reduced the procedure by 10 steps compared with photolithography. Since the process was done in low temperature, there was no pattern transformation and bending problem appeared. It was possible to increase close packing of molecules by SAM, to improve electric field mobility, to decrease contact resistance, and to reduce threshold voltage by using a big dielecric.

• 한국지반공학회지:지반
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• 제12권1호
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• pp.5-20
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• 1996

연약지반 처리방법으로 압밀을 촉진시키고, 이로 인한 전단강도를 증진시키기 위하여 선행압밀하중공법과 병행된 배수공법이 널리 사용되어 오고 있다. 본 연구에서는 배수재가 설치된 연약지반의 압밀과정동안에 유발되는 간극비의 감소로 인한 압축성과 투수계수의 변화를 고려할 수 있는 축대칭 비선형 압밀이론을 제안하였다. 제안된 축대칭 비선형 압밀이론을 명백한(explicit) 유한차분법을 적용하여 해석용 프로그램(AXICON)을 개발하였으며 현장지반의 교란효과나 층으로 이루어진 지반을 해석할 수 있도록 보완하였다. 또한 현장지반의 단계적 시공절차를 고려하여 하중을 적용할 수 있도록 하였다. AXICON 해석결과를 기존의 Hansbo와 Barren의 해석적인 해와 비교 검토하였으며 현장지반에서 계측된 침하량과 과잉 간극수압의 자료와 비교하였다.

• ETRI Journal
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• 제27권6호
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• pp.685-690
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• 2005

DC and RF characteristics of $0.15{\mu}m$ GaAs power metamorphic high electron mobility transistors (MHEMT) have been investigated. The $0.15{\mu}m{\times}100{\mu}m$ MHEMT device shows a drain saturation current of 480 mA/mm, an extrinsic transconductance of 830 mS/mm, and a threshold voltage of -0.65 V. Uniformities of the threshold voltage and the maximum extrinsic transconductance across a 4-inch wafer were 8.3% and 5.1%, respectively. The obtained cut-off frequency and maximum frequency of oscillation are 141 GHz and 243 GHz, respectively. The $8{\times}50{\mu}m$ MHEMT device shows 33.2% power-added efficiency, an 18.1 dB power gain, and a 28.2 mW output power. A very low minimum noise figure of 0.79 dB and an associated gain of 10.56 dB at 26 GHz are obtained for the power MHEMT with an indium content of 53% in the InGaAs channel. This excellent noise characteristic is attributed to the drastic reduction of gate resistance by the T-shaped gate with a wide head and improved device performance. This power MHEMT technology can be used toward 77 GHz band applications.