• Journal of Sensor Science and Technology
• /
• v.4 no.4
• /
• pp.29-40
• /
• 1995

In this paper, the noise equivalent cicuits that is necessary to the formulation of D.C. and noise characteristics, residual component and input capacitance so as to analyze on the noise factors of the SIT is proposed. The simplest noise equivalent circuit is the model representing the mechanism of the SIT and the measured values in this model were found as small as the values of the shot-noise. In the source resistance inserted equivalent circuit is conformed that the shot-noise will be reduced by the negative-feedback effect of the source resistance. In oder to analyze the correct noise reduction factor, I proposed the equivalent circuit which the formulas of the source and drain resistance was induced. In the experiment which affirm the equivalent circuits, the influence of the signal source resistance and output load resistance on the residual component is small and the residual component can be expressed by the equivalent input noise resistance. Moreover, the input capacitance is 13.6 pF when the load resistance is $0{\Omega}$ and the capacitance which does not concern with the SIT operation directly, that is, gate wire etc, is 10pF or so.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.399-399
• /
• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.

• Journal of the Korean GEO-environmental Society
• /
• v.8 no.5
• /
• pp.5-14
• /
• 2007

The quantity of noxious wastes generated by the growth in industrialization and population in all over the world and its potential hazards in subsurface environments are becoming increasingly significant. The extraction of the contaminant from the soil and movement of the water are restricted due to the low permeability and adsorption characteristics of the reclaimed soils. Incorporated technique with PVDs have been used for dewatering from fine-grained soils for the purpose of ground improvement by means of soil flushing and soil vapor extraction systems. This paper is to evaluate several key parameters that affected to the performance of the PVDs specifically with regard to: well resistance of PVD, zone of influence, and smear effects. In the feasibility of contaminant remediation was evaluated in pilot-scale laboratory experiments. Well resistance is affected on the vertical discharge capacity of the PVDs under the various vacuum pressures. The discharge capacity increases consistently in areal extents with higher applied vacuum up to a limiting vacuum pressure. The head values for each piezometer at different vacuum pressures show that the largest head loss occurs within 14 cm of the PVD. Air flow rates and head losses were measured for the PVD placed in the model test box and the gas permeability of the silty soils was calculated. Increasing the equivalent diameter results in a decrease in the calculated gas permeability. It is concluded that the gas permeability determined over the 1,500 to 2,000 $cm^3/s$ flow rates are the most accurate values which yields gas permeability of about 3.152 Darcy.

• Korean Journal of Microbiology
• /
• v.50 no.4
• /
• pp.384-386
• /
• 2014

Pseudomonas aeruginosa is an opportunistic pathogen that inhabits various natural and artificial environments, such as pathogenesis, water, soil and air. They can cause serious problems, such as pathogenic infection. In this study, 220 colonies were isolated from water and soil environment that assumed to be P. aeruginosa using a membrane filter method based on International Organization for Standardization (ISO/NP 16266). Identification of the isolates was determined by physiobiochemical characteristics using newly modified ISO method which includes the resistance to 1,10 phenanthroline test. Only one of 220 presumed P. aeruginosa strains isolated from effluence water using a drain swab was determined as P. aeruginosa-positive by the ISO/NP 16266 method. Subsequently, the resistance to 1,10 phenanthroline test, which was newly proposed by ISO in 2014 and applied in this study, was considered as more precise and improvable method for identification of P. aeruginosa.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.10
• /
• pp.33-46
• /
• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• Journal of the Korean Geotechnical Society
• /
• v.24 no.6
• /
• pp.77-84
• /
• 2008

The existing equations for radial consolidation cannot account for the changes of well resistance with time and cannot predict the appropriate in-situ consolidation curve. In this study, small cylinder cell tests are performed to evaluate the discharge capacity of PVD. Also, a block sample of 1.2 m in diameter and 2.0 m in height was consolidated to observe the change in the drainage capacity with time for three types of PVD. From the test results on a block sample, the drainage curves normalized with initial drainage of each PVD are similar, regardless of the PVD type and the consolidation curve, which is predicted using solutions of radial consolidation based on the discharge capacity measured in a small cylinder cell tests, significantly overestimates the degree of consolidation. The term of well resistance in the radial consolidation solution was back-calculated to fit the consolidation curve of a large block sample and it is defined as the time dependent well resistance factor, L(t). The L(t) was found to be linearly proportional to the dimensionless time factor, Th. It was also shown that the consolidation curve evaluated by using L(t) provides more accurate prediction than the existing solution.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.131-131
• /
• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.6
• /
• pp.34-41
• /
• 1984

MOEN/MO double layer which is to be used It)r the RMOS (refractory metal oxide semiconductor) gate material has been fabricated by means of low temperature reactive sputtering in N2 and Ar mixture. Good Mo2N film was obtained in the volumetric mixture of Ar:N2=95:5. The sheet resistance of the fabricated Mo7N film was about 1.20 - 1.28 ohms/square, which is about an order of magnitude lower than that of polysilicon film, and this would enable to improve the operational speed of devices fabricated with this material. When PSG (phosphorus silicate glass) was used as impurity diffusion source for the source and drain of the RMOSFET in the N2 atmosphere at about 110$0^{\circ}C$, the Mo2N was reduced to Mo resulting in much smaller sheet resistance of about 0.38 ohm/square. The threshold voltage of the RMOSFET fabricated in our experiment was - 1.5 V, and both depletion and enhancement mode RMOSFETs could be obtained.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.6
• /
• pp.876-885
• /
• 2000

A new and simple method is presented for determining the parasitic resistances of MESFET and HEMT from the measured S-parameters under normal active bias without depending on additional DC measurements or iteration or optimization process. The presented method is based on the fact that the difference between source resistance(Rs) and drain resistance(Rd) can be obtained from the measured Z-parameters under zero bias condition. It is possible to define the new internal device including intrinsic device and 3 parasitic resistances by elimination the parasitic inductances and capacitances from the measured S-parameters. Three parasitic resistances are calculated easily from the fact that the real parts of Yint,11 and Yint,12 of intrinsic Y-parameters are zero theoretically and the relations between S-,Z-, Y-matrices. The calculated parasitic resistances using the presented method and successively calculated equivalent circuit parameters give modeled S-parameters which are in good agreement with the measured S-parameters up to 400Hz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.11a
• /
• pp.198-201
• /
• 2002

In this paper, the dependence of Ni-silicide properties such as sheet resistance and cross-sectional profile on the dopants have been characterized. There was little dependence of sheet resistance on the used dopants such as As, P, $BF_{2}$ and $B_{11}$ just after RTP (Rapid Thermal Process). However, the silicide properties showed strong dependence on the dopants when thermal treatment was applied after formation of Ni-silicide. $BF_{2}$ implanted sample shows the best stable property, while $B_{11}$ implanted one was thermally unstable. The main reason of the excellent property of $BF_{2}$ sample is believed to be the retardation of Ni diffusion by the flourine.