• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.78-84
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• 2009

This paper represents the effects of drain bias on the linearity and efficiency of an analog pre-distortion power amplifier(PA) for wideband code division multiple access(WCDMA) repeater applications. For verification, an analog predistorter(APD) with three-branch nonlinear paths for memory-effect compensation is implemented and a class-AB PA is fabricated using a 30-W Si LOMaS. From the measured results, at an average output power of 33 dBm(lO-dB back-off power), the PA with APD shows the adjacent channel leakage ratio(ACLR, ${\pm}$5 MHz offset) of below -45.1 dBc, with a drain efficiency of 24 % at the drain bias voltage($V_{DD}$) of 18 V. This compared an ACLR of -36.7 dEc and drain efficiency of 14.1 % at the $V_{DD}$ of 28 V for a PA without APD.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.5 s.347
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• pp.128-136
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• 2006

In this paper, design and implement 50W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of ideal Doherty power amplifier is distinguishable; however bias control for implementation of Doherty(GDCHD) amplifier is difficult. To solve the problem, therefore, GDCHD(Gate and Drain Control Hybrid Doherty) power amplifier is embodied to drain bias adjustment circuit to Doherty power amplifier with gate bias adjustment circuit. Experiment result shows that $2.11{\sim}2.17\;GHz$, 3GPP operating frequency band, with 57.03 dB gain, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and -40.45 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GDCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than Doherty power amplifier.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.5
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• pp.1592-1596
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• 2010

According to the increase of the channel length with fixed width/length, characteristic curves of drain current as a function of gate bias voltage of indium gallium zinc oxide (IGZO) thin-film transistors moved to a positive direction of gate voltage, and field-effect mobility decreased. In case of fixed length and width of channel, field-effect mobility was lower and subthreshold slope was larger when drain bias voltage was higher. Due to large work function of IGZO, band bending at the junction region between IGZO channel and source/drain electrodes was expected to be in opposite direction to that between silicon and metal electrodes; this could explain the above results.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.27 no.7
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• pp.829-836
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• 2003

Understanding of heat generation in semiconductor devices is important in the thermal management of integrated circuits and in the analysis of the device physics. Scanning thermal microscope was used to measure the temperature and the electric potential distribution on the cross-section of an operating metal-oxide-semiconductor field-effect transistor (MOSFET). The temperature distributions were measured both in DC and AC modes in order to take account of the leakage current. The measurement results showed that as the drain bias was increased the hot spot moved to the drain. The density of the iso-potential lines near the drain increased with the increase in the drain bias.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.6
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

• Advances in nano research
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• v.15 no.3
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• pp.263-275
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• 2023

The electron transport properties of Y-type zigzag branched carbon nanotubes (CNTs) are of great significance for micro and nano carbon-based electronic devices and their interconnection. Based on the semi-empirical method combining tight-binding density functional theory and non-equilibrium Green's function, the electron transport properties between the branches of Y-type zigzag branched CNT are studied. The results show that the drain-source current of semiconducting Y-type zigzag branched CNT (8, 0)-(4, 0)-(4, 0) is cut-off and not affected by the gate voltage in a bias voltage range [-0.5 V, 0.5 V]. The current presents a nonlinear change in a bias voltage range [-1.5 V, -0.5 V] and [0.5 V, 1.5 V]. The tangent slope of the current-voltage curve can be changed by the gate voltage to realize the regulation of the current. The regulation effect under negative bias voltage is more significant. For the larger diameter semiconducting Y-type zigzag branched CNT (10, 0)-(5, 0)-(5, 0), only the value of drain-source current increases due to the larger diameter. For metallic Y-type zigzag branched CNT (12, 0)-(6, 0)-(6, 0), the drain-source current presents a linear change in a bias voltage range [-1.5 V, 1.5 V] and is symmetrical about (0, 0). The slope of current-voltage line can be changed by the gate voltage to realize the regulation of the current. For three kinds of Y-type zigzag branched CNT with different diameters and different conductivity, the current-voltage curve trend changes from decline to rise when the branch of drain-source is exchanged. The current regulation effect of semiconducting Y-type zigzag branched CNT under negative bias voltage is also more significant.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.358-364
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• 2009

This paper shows some variable bias techniques which can improve the power added efficiency(PAE) for the designed power amplifier. Some simulations have been done to get the effect of the bias change, and variable bias is adopted to get the higher efficiency for dual mode amplifier which generates two different output power levels. With drain bias change and a fixed gate bias, the amplifier shows PAE improvement compared to the fixed bias amplifier. In addition, this paper analyzed nonlinear distortion of the power amplifier and has used the digital predistortion which can result in 10dB ACPR improvement for the dual band amplifier.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1315-1317
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• 1998

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshold voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate bias stressing and under the gate and drain bias stressing. Also, we have quantitatively analized the degradation phenomena using by analytical method. we have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the poly-Si is prevalent in gate and drain bias stressed device.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.