• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.6
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• pp.1214-1218
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• 2006

This paper presents method to speed up processing time in construction of panoramic images. The method based on invariant feature uses image down-scaling and image edge information. Reducing image size and applying feature descriptor to image portions superimposed with edge causes to reduce the number of features and to improve processing speed. In the experiments, it was shown that the proposed method was 3.26$\sim$13.87% shorter in processing time than the exiting method fer 24-bit color images of 640$\times$480 size.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.45-47
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• 2008

This paper describes development of PMSG wind power system model using wind turbine simulator and matrix converter. The wind turbine simulator, which consists of an induction motor with vector drive, calculates the output torque of a specific wind turbine using simulation software and sends the torque signal to the vector drive after scaling down the calculated value. The operational feasibility of interconnected PMSG system with matrix converter was verified by computer simulations with PSCAD/EMTDC software. The simulation results confirm that matrix converter can be effectively applied for the PMSG system.

• Journal of Mechanical Science and Technology
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• v.19 no.6
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• pp.1268-1279
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• 2005

The current method for pavement sign marking operations is labor-intensive and very dangerous due to the exposure of workers to passing traffic. It also requires blocking traffic for a long period of time resulting serious traffic jam. This paper deals with the development of a robotic system for automating the pavement sign painting operations. The robotic system consists of gantry frame equipped with transverse drive rail and automatic paint spray system. The workspace of the gantry robot is extended to one-lane width with the transverse rail system. This research also includes the development of font data structures that contain the shape information of pavement signs, such as Korean letters, English letters and symbols. The robot path is generated with this font data through the procedures of scaling up/down and partitioning the signs to be painted depending on the workspace size.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.34-40
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• 2018

Traditionally, many researchers have conducted research on terahertz technology utilizing optical devices such as lasers. However, nanometer-scale electronic devices using silicon or III-V compound semiconductors have received significant attention regarding the development of a terahertz system owing to the rapid scaling down of devices. This enables an operating frequency of up to approximately 0.5 THz for silicon, and approximately 1 THz for III-V devices. This article reviews the recent trends of terahertz monolithic integrated circuits based on several electronic devices such as CMOS, SiGe BiCMOS, and InP HBT/HEMT, and a particular quantum device, an RTD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2106-2115
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• 1994

As a pre processing for an edge detection process. edge preserving smoothing algorithm is proposed. For this purpose we used the interpolation method using B-spline basis function and scaling of digital images. By approximation of continuous function from descrete data using B-spline basis function. undetermined data between two sample can be computed. so that they smooth the surfaces of objects. Some edges having mainly low frequency components are detected using down scaling of the images. Edge maps from proposed pre processed images are hardly affected by the varying space constants($\sigma$) and threshold values used in detecting zero-crossing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.1-8
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• 2005

The gate length-dependence of cutoff frequency is modeled by using scaling parameter equations of equivalent circuit parameters extracted from measured S-parameters of Nano-scale MOSFETs. It is observed that the modeled cutoff frequency initially increases with decreasing gate length and then the rate of increase becomes degraded at further scale-down. This is because the extrinsic charging time slightly decreases, although the intrinsic transit time greatly decreases with gate length reduction. The new gate length-dependent model will be very helpful to optimize RF performances of Nano-scale MOSFETs.

• Journal of Korea Society of Industrial Information Systems
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• v.4 no.4
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• pp.1-6
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• 1999

When continuous media are transmitted over the communication networks, asynchrony which can not maintain temporal relationships among packets my occur due to a random transit delay. There exist two types of synchronization schemes ; for guaranteed or non-guaranteed resource networks. The former which applies a resource reservation technique maintains delay characteristics however, the latter supply a best-effort service. In this paper, I propose a intra-media synchronization scheme to transmit continuous media on general networks not guaranteeing a bounded delay time. The scheme controls transmission times of the packets by estimating next delay time with the delay distribution So, the arriving packets my be maintained within a limited delay boundary, and playout will be performed after buffering to smoothen small delay variations. To prevent network congestion and maintain minimum quality of service the transmitter performs media scaling-down by dropping the current packet when informed excessive delay from the receiver.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Journal of Korea Multimedia Society
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• v.13 no.1
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• pp.30-37
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• 2010

Many embedded real - lime systems have adopted processors supported with dynamic voltage scal-ing(DVS) recently. Power is one of the important metrics for Optimization in the design and operation of embedded real-time systems. We can save considerable energy by using slowdown of processor sup-ported with DVS. In this paper, we improved the previous algorithm at a point of view of time complexity to calculate task slowdown factors for an efficient energy consumption in embedded real-time systems with task synchronization. We grasped the properties of the previous algorithm having $O(n^{2})$ time complexity through mathematical analysis and s simulation. Using its properties we proposed the improved algorithms with O(nlogn) and O(n) time complexity which have the same performance as the previous algorithm has.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12C
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• pp.1142-1148
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• 2007

In this paper, we propose ASLM (Adaptive Selective Mapping; ASLM) scheme based on peak observation for PAPR (Peak-to-Average Power Ratio) reduction of OFDM (Orthogonal Frequency Division Multiplexing) signals. The proposed scheme is composed of three steps: peak scaling, sequence selection, and SLM procedures. In the first step, the peak signal samples in the IFFT (Inverse Fast Fourier Transform) outputs of the original input sequence are scaled down. In the second step, the sub-carrier positions where the power difference between the original input sequence and the FFT output of the scaled signal is large, are identified. Then, the phase sequences having the maximum number of phase-reversed sequence words only for these positions are selected. Finally, the generic SLM procedure is performed by using only the selected phase sequences for the original input sequence. Simulation results show that the proposed scheme significantly reduces the complexity in terms of IFFT and PAPR calculation than the conventional SLM, while maintaining the PAPR reduction performance.