• 한국우주과학회:학술대회논문집(한국우주과학회보)
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• 한국우주과학회 2008년도 한국우주과학회보 제17권2호
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• pp.34.3-34.3
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• 2008

Relative navigation system is presented using measurements from a single-channel global positioning system (GPS) simulator. The objective of this study is to provide real-time relative navigation results as well as absolute navigation results for two formation flying satellites separated about 1km in low earth orbit. To improve the performance, more accurate dynamic model and modified relative measurement model are developed. This modified method prevents non-linearity of the measurement model from degrading precision by applying linearization about the states from absolute navigation algorithm not about a priori states. Furthermore, absolute states are obtained using ion-free GRAPHIC pseudo-ranges and precise relative states are provided using double differential carrier-phase data based on Extended Kalman Filter. The software-based simulation is performed and achieved meter-level precision for absolute navigation and millimeter-level precision for relative navigation. The absolute and relative accuracies at steady state are about 0.77m and 4mm respectively (3D, r.m.s.). In addition, Integer ambiguity algorithm (LAMBDA method) improves simulation performances.

• Wind and Structures
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• 제11권5호
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• pp.345-359
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• 2008

An experimental investigation of the flow over the rectangular body located in close proximity to a ground board was reported using the particle image velocimetry (PIV) technique. The present experiments were conducted in a closed-loop open surface water channel with the Reynolds number, $Re_H=1.2{\times}10^4$ based on the model height. In addition to the PIV measurements, flow visualization studies were also carried out. The PIV technique provided instantaneous and time-averaged velocity vectors map, vorticity contours, streamline topology and turbulent quantities at various locations in the near wake. In the vertical symmetry plane, the upperbody flow is separated from the sharp top leading edge of the model and formed a large reverse flow region on the upper surface of the model. The flow structure downstream of the model has asymmetric double vortices. In the horizontal symmetry plane, identical separated flow regions occur on both vertical side walls and a pair of primary recirculatory bubbles dominates the wake region.

• 대한안전경영과학회지
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• 제17권1호
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• pp.203-213
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• 2015

Recently, online grocery shopping has been increasing with the development of internet, mobile, and IT technology due to the proportion of consumers changes like increasing single households and double-income couples. Therefore, online sales from distributors with offline stores have also increased, and the offline retailers are facing their limits in dealing with store-based online channel they have carried out. Domestic offline retailers benchmarked overseas advanced retailers to solve this problem by reviewing about developing the online-only distribution center. However, much investment is needed in order to operate the distribution center with the new concept from abroad. In this study, we have reviewed the current online grocery market trend and the theory related to developing distribution system of the online mall. For offline retailers, we have reviewed the case which developed the distribution center applied to the nation's first online-only distribution center. The purpose of this study is reducing trial and error for local retailers in developing online-only distribution centers and suggesting ways to improve investment effect.

• Transactions on Electrical and Electronic Materials
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• 제8권3호
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• pp.139-142
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• 2007

Organic field-effect transistor (FET) based on a copper Phthalocyanine (CuPc) material as an active layer and a $SiO_2$ as a gate insulator were fabricated and analyzed. We measured the typical FET characteristics of CuPc in air. The electrical characteristics of the CuPc FET device were analyzed by a Maxwell-Wagner model. The Maxwell-Wagner model employed in analyzing double-layer dielectric system was helpful to explain the C-V and I-V characteristics of the FET device. In order to further clarity the channel formation of the CuPc FET, optical second harmonic generation (SHG) measurement was also employed. Interestingly, SHG modulation was not observed for the CuPc FET. This result indicates that the accumulation of charge from bulk CuPc makes a significant contribution.

• 대한전자공학회논문지
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• 제26권5호
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• pp.38-45
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• 1989

보론이 100ppm으로 도우핑된 비정질 실리콘을 이용한 쌍극 박막 트랜지스터를 CVD 방법으로 제작하여 전기적 특성을 조사하였다. 쌍극 박막 트랜지스터에 인가한 트레인 전압이 증가하면 정공채널의 드레인 전류는 전자와 정공의 주입에 의해 크게 증가한다. 또한 게이트 전압의 인가 시간에 따른 드레인 전류는 streched exponential로 감소하는데, 이는 전자축적층에 의해 생기는 댕글린 본드 밀도의 변화가 수소의 확산과 동일한 시간 의존성을 갖는 것을 의미한다. 이러한 실험 결과로 부터 보론이 도우핑된 수소화된 비정질 실리콘에 게이트 전압을 인가하거나, 빛 조사시 도우핑 효율이 변화함을 알 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• 대한기계학회논문집
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• 제9권2호
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• pp.202-212
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• 1985

본 논문에서는 이러한 연구의 첫단계로 Gosman과 Ideriah가 다룬 TEACH-2E전 산프로그램을 모체로 하여 본 논문의 문제에 적합하도록 수정하여 사용하였다. 그러 나 기본적인 k-.epsilon.난류모델은 수정하지 않았다. 한편, 본 논문에서는 열선풍속계를 이용하여 평균 속도분포 및 난류특성을 계측하고 계산결과와 비교하였다. 이를 통하 여 표준형 k-.epsilon.모델을 이용한 TEACH-2E코드의 특성을 파악하고 이를 위한 실험 데이터 를 확보하는데 중점을 두었다.

• 대한전자공학회논문지SD
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• 제39권1호
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• pp.58-66
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• 2002

Tapered 방향성 가중 결합 음향파 도파로를 이용하여 음향광학형 파장가변 광 필터를 LiNbO₃와 Ti 이중 확산 공정 기술을 이용하여 제작하였다. 1551.1㎚ 파장의 TE, TM 입사 편광모드와 173.58㎒ 35㎽ RF구동 신호에 대해서 각각 -14.29㏈, -14.99㏈ 부 모드 억압과 61%, 86% 변환효율이 측정되었다. 파장변화율과 통과 대역폭은 8.6㎚/㎒ 1.8㎚로 측정되었으며, 스위칭 속도는 2.82㎲로 측정되었다. 2.5㎚ 채널 간격에 대해서 약 -l4㏈누화 레벨이 측정되었으며, 부 모드와 채널 간격이 누화에 매우 큰 영향을 미치고있음을 확인하였다.