• ETRI Journal
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• 제24권4호
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• pp.270-279
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• 2002

We present a self-consistent numerical method for calculating the conduction-band profile and subband structure of AlGaN/GaN single heterojunctions. The subband calculations take into account the piezoelectric and spontaneous polarization effect and the Hartree and exchange-correlation interaction. We calculate the dependence of electron sheet concentration and subband energies on various structural parameters, such as the width and Al mole fraction of AlGaN, the density of donor impurities in AlGaN, and the density of acceptor impurities in GaN, as well as the electron temperature. The electron sheet concentration was sensitively dependent on the Al mole fraction and width of the AlGaN layer and the doping density of donor impurities in the AlGaN. The calculated results of electron sheet concentration as a function of the Al mole fraction are in excellent agreement with some experimental data available in the literature.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권2호
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• pp.74-79
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• 2003

The method of the analysis of the base Gummel number of the BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of NPN BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data and the transistor saturation current of PNP BJT shows an averaged relative error of 9.2% compared with the measured data

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1622-1624
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• 2007

In order to realize effective p-type doping in ZnO thin films, ZnO films were deposited on P-doped Silayers by RF-magnetron sputter deposition technique and annealed at various temperatures. The result indicated that ZnO film annealed at $700^{\circ}C$ showed p-type conduction with a high carrier concentration in the order of $10^{19}\;cm^{-3}$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.243-246
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• 2001

Thyristor devices have 3-dimensional complicated structure and were sensitive to temperature characteristics. Therefore, it was difficult to optimize thyristor devices design. We have to consider many design parameter to characterize, and trade-off relations. The important parameters to design thyristor devices are cathode structure, effective line width, cathode-emitter shunt structure, gate structure, doping profile and carrier lifetime. So, we must consider that these design parameters were not acted separately. However, there are many difficulties to determine optimized design parameters by experiment. So, We used specific design software to design thyristor devices, and estimated the thyristor devices characteristics.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.178-178
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• 1999

Low temperature Si epitaxy can provide flexibility for a device designer to tailor or optimize the device performance. It is better method for controlling the doping thickness, concentration and profile than ion implantation and diffusion. But there is a limited growth thickness in this method. At a given temperature, the film grows epitaxially for a certain limiting thickness(hepi) and becomes amorphous. The transition from crystalline Si to amorphous Si is abrupt. In this study, Si film was deposited by ion beam sputter deposition on Si (0001) above a limiting thickness and measure the strain in the interface between crystalline Si and amorphous Si. The strain was compressive and the maximum value was about 2%.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.12-17
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• 2004

The body-tied FinFETs (bulk FinFETs) implemented on bulk Si substrate were characterized through 3-dimensional device simulation. By controlling the doping profile along the vertical fin body, the bulk FinFETs can be scaled down to sub-30 nm. Device characteristics with the body shape were also shown. At a contact resistivity of $1{\times}10^{-7}\;{\Omega}\;cm^2$, the device with side metal contact of fin source/drain showed higher drain current by about two. The C-V results were also shown for the first time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 추계학술대회 논문집
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• pp.14-17
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• 1992

To analyze Nonvolatile SNOSFET(polySilicon-Nitride-Oxide-Semiconductor Field Effect Transistor) memory device, two dimensional numerical computer simulation program was developed. The equation discretization was performed by the Finite difference method and the solution was derived by the Iteration method. The doping profile of n-channel device which was fabricated by 1Mbit CMOS process was observed. The electrical potential and the carrier concentration distribution to applied bias condition were observed in the inner of a device. As a result of the write and the erase to memory charge quantity, the threshold voltage shift is expected. Therefore, without device fabrication, the operating characteristics of the device was observed under various the processing and the operating condition.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.106-110
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• 1997

A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.

• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.463-463
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• 2013

This paper reports the synthesis and characterization of ZnO:Ga nano-structures deposited on Au/SiNx/Si(001) by radio-frequency sputtering. The effect of the temperature on the microstructure of the as-grown ZnO:Ga thin films was examined. The growth mode of ZnO:Ga nano-structures can be explained by the profile coating, i.e. the ZnO nano-structures were formed with a morphological replica of Au seeds. Initially, the ZnO:Ga nano-structures were overgrown on top of Au nano-crystals. Small ZnO:Ga nano-dots were then nucleated on hexagonal ZnO:Ga discs.