• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2003년도 학술대회지
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• pp.402-402
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• 2003

• Transactions on Electrical and Electronic Materials
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• 제6권5호
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• pp.225-228
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• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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• pp.435-437
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• 2002

Polishing of copper, a process called copper chemical mechanical polishing, is a critical, intermediate step in the planarization of silicon wafers. During polishing, the electrodeposited copper films are removed by slurries: and the differential polishing rates between copper and the surrounding silicon dioxide leads to a greater removal of the copper. The differential polishing develops dimples and furrows; and the process is called dishing and erosion. In this work, we present the results of experiments on dishing and erosion of copper-CMP, using patterned silicon wafers. Results are analyzed for the pattern factors and properties of the copper layers. Three types of pads - plain, perforated, and grooved - were used for polishing. The effect of slurry chemistries and pad soaking is also reported.

• 한국재료학회지
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• 제22권11호
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• pp.587-590
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• 2012

Recently, the demand for the miniaturization of package substrates has been increasing. Technical innovation has occurred to move package substrate manufacturing steps into CMP applications. Electroplated copper filled trenches on the substrate need to be planarized for multi-level wires of less than $10{\mu}m$. This paper introduces a chemical mechanical planarization (CMP) process as a new package substrate manufacturing step. The purpose of this study is to investigate the effect of surfactant on the dishing and erosion of Cu patterns with the lines and spaces of around $10/10{\mu}m$ used for advanced package substrates. The use of a conventional Cu slurry without surfactant led to problems, including severe erosion of $0.58{\mu}m$ in Cu patterns smaller than $4/6{\mu}m$ and deep dishing of $4.2{\mu}m$ in Cu patterns larger than $14/16{\mu}m$. However, experimental results showed that the friction force during Cu CMP changed to lower value, and that dishing and erosion became smaller simultaneously as the surfactant concentration became higher. Finally, it was possible to realize more globally planarized Cu patterns with erosion ranges of $0.22{\mu}m$ to $0.35{\mu}m$ and dishing ranges of $0.37{\mu}m$ to $0.69{\mu}m$ by using 3 wt% concentration of surfactant.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.525-526
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• 2007

Over-polishing is required to completely remove the material of top surface across whole wafer, in spite of a local dishing problem. This paper introduces the two-step CMP process using protective layer and high selectivity slurry, to reduce dishing amount and variation. The 30nm thick protective oxide layer was deposited on the pattern, and then polished with low selectivity slurry to partially remove the projected area while suppressing the removal rate of the recessed area. After the first step CMP process, high selectivity slurry was used to minimize the dishing amount and variation in pattern structure. Experimental result shows that two-step CMP process can be successfully applicable to reduce the dishing defect generated in over-polishing.

• 한국전기전자재료학회논문지
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• 제18권4호
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• pp.321-326
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• 2005

Chemical mechanical polishing(CMP) process is essential technology to be applied to manufacturing the dielectric layer and metal line in semiconductor devices. It has been known that overpolishing in CMP depends on pattern selectivity as a function of density and pitch, and use of fixed abrasive pad(FAP) is one method which can improve the pattern selectivity. Thus, dishing & erosion defects can be reduced. This paper introduces the manufacturing technique of FAP using hydrophilic polymers with swelling characteristic in water and explains the self-conditioning phenomenon. When applied to tungsten blanket wafers, the FAP resulted in appropriate performance in point of uniformity, material selectivity and roughness. Especially, reduced dishing and erosion was observed in CMP of tungsten pattern wafer with the proposed FAP.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.376-377
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• 2006

Chemical Mechanical Planarization (CMP) has emerged as an enabling technology for the manufacturing of multi-level metal interconnects used in high-density Integrated Circuits (IC). Recently, multi-level structures have been also widely used m the MEMS device such as micro engines, pressure sensors, micromechanical fluid pumps, micro mirrors and micro lenses. Especially, among the thin films available in IC technologies, polysilicon has probably found the widest range of uses in silicon technology based MEMS. This paper presents the characteristic of polysilicon CMP for multi-level MEMS structures. Two-step CMP process verifies that is possible to decrease dishing amount with two type of slurries characteristics. This approach is attractive because two-step CMP process can be decreased dishing amount considerably more then just one CMP process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.125-126
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• 2005

Recently semiconductor devices are required more smaller scale and more powerful performance. For smaller scale of device, multilayer structure is proposed. And, for the higher performance, interconnection material is change to copper, because copper has high EM(Electro-migration)and low resistivity. Then copper CMP process is a great role in a multilayer formation of semiconductor. Copper process is different from aluminum process. ECP process is one of the copper processes. In this paper, we focused on the defects tendency by copper thickness which filled using ECP process. we observed hump high and dishing. Conclusively, hump hight reduced at copper thickness increased Also dishing reduced.

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.39-45
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• 2012

Cu-Cu 패턴의 직접접합 공정을 위하여 Buffered Oxide Etch(BOE) 및 Hydrofluoric acid(HF)의 습식 조건에 따른 Cu와 $SiO_2$의 식각 특성에 대한 평가를 수행하였다. 접촉식 3차원측정기(3D-Profiler)를 이용하여 Cu와 $SiO_2$의 단차 및 Chemical Mechanical Polishing(CMP)에 의한 Cu의 dishing된 정도를 분석 하였다. 실험 결과 BOE 및 HF 습식 식각 시간이 증가함에 따라 단차가 증가 하였고, BOE가 HF보다 더 식각 속도가 빠른 것을 확인하였다. BOE 및 HF 습식 식각 후 Cu의 dishing도 식각시간 증가에 따라 감소하였다. 식각 후 산화막 유무를 알아보기 위해 Cu표면을 X-선 광전자 분광법(X-ray Photoelectron Spectroscopy, XPS)를 이용하여 분석 한 결과 HF습식 식각 후 BOE습식 식각보다 Cu표면산화막이 상대적으로 더 얇아 진 것을 확인하였다.

• 한국기계가공학회지
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• 제2권4호
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• pp.17-24
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• 2003

Chemical mechanical polishing(CMP) has been applied for planarization of topography after patterning process in semiconductor fabrication process. Tungsten CMP is necessary to build up interconnects of semiconductor device. But the tungsten dishing and the oxide erosion defects appear at end-point during tungsten CMP. It has been known that the generation of dishing and erosion is based on the over-polishing time, which is determined by pattern selectivity. Fixed abrasive pad takes advantage of decreasing the defects resulting flam reducing pattern selectivity because of the lower abrasive concentration. The manufacturing technique of fixed abrasive pad using hydrophilic polymers is introduced in this paper. For application to tungsten CMP, chemicals composed of oxidizer, catalyst, and acid were developed. In comparison of the general pad and slurry for tungsten CMP, the fixed abrasive pad and the chemicals resulted in appropriate performance in point of removal rate, uniformity, material selectivity and roughness.