• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.361-364
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• 2000

One of the problems using DCR(Direct Conversion Receiver) are DC offset, poor channel selectivity. APDP(Anti Parallel Diode Pair) can be good candidate for DCR frequency mixer due to its inherent End harmonic suppression. APDP shows good IP2 and DC suppression. This paper describe single APDP LO power characteristics, IP2, and receiver structure utilizing APDP frequency mixer

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.154-157
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• 2000

One of the problems using DCR(Direct Conversion Receiver) type architecture are DC offset, Poor channel selectivity. APDP(Anti Parallel Diode Pair) can be mood candidate for the DCR frequency mixer due to its inherent 2nd harmonic suppression. APDP shows good IP2 and DC suppression. This paper describes single APDP LO power characteristics, IP2, and receiver structure utilizing APDP frequency mixer.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2002.11a
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• pp.9-14
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• 2002

Direct-conversion receiver(DCR) architecture has superior advantages in size, cost, and power over superheterodyne receiver architectures. However, the use of direct-conversion receiver architecture has been limited due to the direct-current offset noise. The ac coupling, which is used to overcome the direct-current offset noise, causes an inter-symbol interference(ISI), whose effects can be effectively mitigated using an equalizer. In this paper, the performance of a direct-conversion receiver with ac coupling in the presence of direct-current offset is analyzed via computer simulation. The simulation result shows that by using decision feedback equalizer with LMS(Least Mean Square) algorithm, signal-to-noise ratio loss of the direct-conversion receiver compared to the idea receiver can be reduced to less than 1㏈ for corner frequencies as large as 10% of the symbol rate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2267-2272
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• 2009

The six-port direct conversion receiver front-end that is comprised of a carrier recovery and a phase shifter, which gets the same structure with six-port phase correlator using the multi-layer coupled line, was designed and fabricated in this paper. The six-port element that is comprised of the power divider and the hybrid coupler is designed by multi-layer coupled line structure. The multi-coupled structure is utilized as the basic structure in receiver phase correlator, carrier recovery circuit and phase shifter. The receiver front-end with the same multi-layer coupled line structure for the receiver elements shows the simple structure and no difficulty in integration. The fabricated multi-layer coupled six-port receiver front-end re-generates the carrier signal with a constant phase and demodulates the PSK transmission signal.

• ETRI Journal
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• v.36 no.1
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• pp.12-21
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• 2014

In this paper, we propose a new digital blind in-phase/quadrature-phase (I/Q) mismatch compensation technique for image rejection in a direct-conversion receiver (DCR). The proposed image-rejection circuit adopts DC offset cancellation and a sign-sign least mean squares (LMS) algorithm with a unique step size adaptation both for a fast and precise I/Q mismatch estimation. In addition, several performance-optimizing design considerations related to accuracy, speed, and hardware simplicity are discussed. The implementation of the proposed circuit in an FPGA results in an image-rejection ratio (IRR) of 65 dB, which is the best performance with modulated signals, along with an adaptation time of 0.9 seconds, which is a tenfold increase in the compensation speed as compared to previously reported circuits. The proposed technique will be a promising solution in the area of image rejection to increase both the speed and accuracy of future DCRs.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.3-10
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• 2014

Direct conversion receiver(DCR) gets noticed for integration and cost reduction of wireless communication systems instead of the heterodyne receiver which uses complex filter. But DCR has several factors in performance degradation. One of them is I/Q imbalance phenomenon, that is amplitude and phase mismatch between real and imaginary part of receiver. Accordingly, researches are being carried to improve the I/Q imbalance problem. However, the tendency of the broaden bandwidth of communication systems, low pass filter(LPF) mismatch problem affects severely in I/Q mismatch phenomenon at the DCR. To study this problem, we generated 10MHz broadband signal and shifted it ${\pm}8MHz$ from the center frequency. The signal is affected by LPF mismatch and it appears as frequency selective distortion. Thus, LPF mismatch model is added to I/Q imbalance model which conventionally dealt with amplitude and phase mismatches. In addition, we proposed the compensation method for each factors of mismatch. As the simulation results, the proposed I/Q mismatch compensator resolves the frequency selective distortion which occurred by the existing LPF mismatch.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1104-1111
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• 2003

The paper presents an algorithm for the compensation of gain and phase imbalances to exist between I-phase and Q-phase signal at direct conversion receiver. We propose a gain and phase imbalances blind equalization compensation algorithm by using variable step-size adaptive loop at direct conversion receiver. The blind equalization schemes have trade-off between convergence speed and jitter effect for the compensation of gain and phase imbalance. We propose the variable step-size adaptive loop method, which varies the loop coefficients according to errors, for recovering these problem. By using variable step-size adaptive loops, we propose to speed up the convergence process and reduce the jitter effect and simulation results show that the algorithm compensates signal loss and speeds up convergence time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.15-23
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• 2007

A simple six-port direct conversion QPSK receiver which is made up of a six-port phase correlator, a signal power detector, and I/Q channel signal de-modulator is designed and implemented in this paper. The output phase signals of six-port phase correlator are also analysed. On the basis of $90^{\circ}C$ phase relation among the six-port phase correlator output signals, the QPSK de-modulation circuit is designed by a simple circuit. The six-port phase correlator is made up of $90^{\circ}$ hybrid branch line and power detector. The six-port phase correlator, which is designed in frequency range of 11.7 to 12.0 GHz, gets the phase error characteristics less than $5^{\circ}$. By considering matching network and amplitude balance in the designed fiequency range, the designed six-port direct conversion QPSK receiver demodulates the I and Q signals with performance less than $5^{\circ}$ phase error.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1071-1077
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• 2010

The six-port phase correlator using lumped elements was designed and fabricated in this paper, also the receiving performance of L-band direct conversion receiver using lumped six-port phase correlator element was analyzed. The proposed L-band lumped six-port phase correlator element was composed of a resistive power divider and the twist-wire coaxial cables. The proposed lumped six-port structure provides the small-sized configuration and wide-band characteristics. The performance of the L-band lumped direct conversion receiver structure was measured under the conditions of 1.69 GHz frequency for LO-CW signal and RF-QPSK signal, which are input signals for the lumped six-port phase correlator element. The direct conversion receiving structure using the proposed lumped six-port phase correlator element can recovered the good digital I/Q signal.