• 조명전기설비학회논문지
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• 제26권6호
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• pp.87-93
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• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• 한국항공운항학회지
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• 제19권4호
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• pp.18-23
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• 2011

Generally, the digital circuit card can be tested by automatic test equipment using LASAR(Logic Automated Stimulus and Response). This paper proposes the ROM data extracting algorithm which can test the digital circuit card that consists usually ROMs. We are implemented of the proposed fault detecting program by LabWindow/CVI 8.5 and the digital automatic test instrument with NI-VXI(National Instrument - Versa Bus Modular Europe eXtentions for Instrumentation) card. We also make an interface circuit board connecting the digital test instrument and the digital circuit card. It shows the good performance of getting the data from ROMs.

• 대한전기학회논문지:전력기술부문A
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• 제52권8호
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• pp.444-449
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• 2003

In this paper present Autonomous Adaptive Digital Over Current Relay for distribution networks which acts autonomous setting using the short circuit impedance measured by relay of power systems. Automation of relay setting is one of the basic requirements for distribution automation, although manual relay setting is used at present. The short circuit impedance from a power source in distribution networks essential for the Autonomous Relay Setting changes frequently in distribution networks. In this paper the short circuit impedance is calculated with voltage and current measured in real time operation of digital relay using the Recursive Least Squares. A new method of digital relay setting is introduced using the the short circuit impedance and load current.

• IEIE Transactions on Smart Processing and Computing
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• 제2권4호
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• 한국분말재료학회지
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• 제19권4호
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• pp.297-303
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• 2012

In this study, voltammetry system for realizing high sensitivity nano-labeled sensor of detecting heavy metals was designed, and optimal system operating conditions were determined. High precision digital to analog converter (DAC) circuit was designed to control applied unit voltage at working electrode and analog to digital converter (ADC) circuit was designed to measure the current range of $0.1{\sim}1000{\mu}A$ at counter electrode. Main control unit (MCU) circuit for controlling voltammetry system with 150 MHz clock speed, main memory circuit for the mathematical operation processing of the measured current value and independent power circuit for analog/digital circuit parts to reduce various noise were designed. From result of voltammetry system operation, oxidation current peaks which are proportional to the concentrations of Zn, Cd and Pb ions were found at each oxidation potential with high precision.

• 디지털산업정보학회논문지
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• 제9권2호
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1692-1695
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• 2007

We describe the image enhancement method of applying two spatial filters with different characteristics adaptively. An adaptive method is introduced so that sharpness enhancement is performed only in regions where the image exhibits significant dynamics, while noise reduction is achieved in smooth regions. Simulation results show that the proposed method improved the image quality.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
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• pp.58-61
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• 2003

This paper proposes e-Learning environments far digital circuit experiment. The e-Learning environments are implemented as a WBT system that includes the circuits monitoring system and the students management system. In the WBT client-server system, the instructor represents the server and students represent clients. The client computers are equipped with a digital circuit training board and connected to the server on the World Wide Web. The training board consists of a Programmable Logic Device (PLD) and measuring instruments. The instructor can reconfigure the PLD with various circuit designs from the server so that students can investigate signals from the training board. The instructor can monitor the progress of the students using Joint Test Action Grouo(JTAG) technology. We implement the WBT system and a courseware fo digital circuits and evaluation the environments.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1483-1486
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• 2006

We describe the contrast enhancement of images using an APL(Average Picture Level) in an AC-PDP. A CEC(Contrast Enhancement Curve) determined by the APL was applied to enhance the contrast of images depending on the dominant gray levels. The most effective advantage of the proposed method is that it is easier to adjust the dynamic ranges to be enhanced with good quality and implement in a hardware system. The simulation result shows that the proposed method enhanced the contrast of given images significantly and kept the original brightness except the specific area of them compared to the HE(Histogram Equalization).