• 대한전자공학회논문지
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• 제23권6호
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• pp.902-907
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• 1986

A real-time microprogrammable digital signal processor is designed and implemented using the bit-slice logic, a parallel multiplier, 74 series TTLs and MOS memories. A microinstruction set for the processor is defined and an application program development system is constructed. For its performance evalution, a digital filter and FFT are implemented with this digital signal processor. It is proved that this processor is faster than commrcially available single chip digital signal processors such as \ulcornerD 7720, AMI 2811, enabling very high speed digital signal processing.

• 한국인터넷방송통신학회논문지
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• 제18권3호
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• pp.177-183
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• 2018

현재, 영상처리, 음성처리, 필터링, 등화 등의 분야에 디지털 신호처리 시스템이 광범위하게 쓰이고 있다. 더불어, 디지털 신호처리 시스템을 구성하는 디지털 신호처리 프로세서의 성능에 지대한 영향을 미치는 DRAM에 대한 연구가 산업계와 학계에서 활발하게 진행되고 있다. 따라서, 모의실험을 통하여 디지털 신호처리 프로세서의 성능에 대한 신뢰할만한 결과를 얻기 위하여, 보다 정확한 DRAM 모델을 갖추는 것이 중요하다. 본 논문에서는 싸이클 단위로 정확하게 동작하는 DRAM 시뮬레이터와 연동할 수 있는 디지털 신호처리 프로세서 모의실험기를 개발했다. 그리고 UTDSP 디지털 신호처리 벤치마크를 개발한 모의실험기에 대한 입력으로 하여, DRAM이 디지털 신호처리 프로세서의 성능에 끼치는 영향을 분석하였다.

• 한국인터넷방송통신학회논문지
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• 제13권4호
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• pp.171-177
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• 2013

최근에 이르러, 고속의 3차원 그래픽 렌더링, 비디오 화일 포맷의 변환, 압축, 암호화 및 암호해독 처리를 위한 디지털 신호처리 시스템의 성능이 고도화가 요구된다. 현재 범용 컴퓨터 시스템을 구축할 때 성능을 높이기 위하여 멀티코어 프로세서가 널리 이용되고 있으므로, 디지털 신호처리 프로세서 역시 멀티코어 프로세서 구조를 채택하여 디지털 신호처리 시스템에서 높은 성능을 얻을 수가 있다. 본 논문에서는 코어의 유형 및 개수가 멀티코어 디지털 신호처리 프로세서의 성능에 미치는 영향을 분석하기 위하여, 2 개에서 16 개로 구성되는 멀티코어 디지털 신호처리 프로세서에 대하여, UTDSP 벤치마크를 입력으로 하는 모의실험을 수행하였다. 이 때, 멀티코어 디지털 신호처리 프로세서를 구성하는 단위 코어로서, 단순한 RISC형부터 다양한 명령어 윈도우의 크기를 갖는 순차 및 비순차 실행 수퍼스칼라 코어에 걸쳐 광범위한 모의실험을 수행하여 그 성능을 분석하였다.

• 한국소음진동공학회논문집
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• 제15권8호
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• pp.954-961
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• 2005

This paper is concerned with the implementation of auto-tuning positive position feedback controller using a digital signal processor and microcontroller. The main advantage of the positive position feedback controller is that it can control a natural mode of interest by tuning the filter frequency of the positive position feedback controller to the natural frequency of the target mode. However, the positive position feedback controller loses its advantage when mistuned. In this paper, the fast fourier transform algorithm is implemented on the microcontroller whereas the positive position feedback controller is implemented on the digital signal processor. After calculating the frequency which affects the vibrations of structure most, the result is transferred to the digital signal processor. The digital signal processor updates the information on the frequency to be controlled so that it can cope with both internal and external changes. The proposed scheme was installed and tested using a beam equipped with piezoceramic sensor and actuator. The experimental results show that the auto-tuning positive position feedback controller proposed in this paper can suppress vibrations even when the target structure undergoes structural change thus validating the approach.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2005년도 춘계학술대회논문집
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• pp.498-503
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• 2005

This paper is concerned with the implementation of adaptive positive position feedback controller using a digital signal processor and microcontroller The main advantage of the positive position feedback controller is that it can control a natural mode of interest by tuning the filter frequency of the positive position feedback controller to the natural frequency of the target mode. However, the positive position feedback controller loses its advantage when mistuned. In this paper, the fast fourier transform algorithm is implemented on the microcontroller whereas the positive position feedback controller is implemented on the digital signal processor. After calculating the frequency which affects the vibrations of structure most the result is transferred to the digital signal processor. The digital signal processor updates the information on the frequency to be controlled so that it can cope with both internal and external changes. The proposed scheme was installed and tested using a beam equipped with piezoceramic sensor and actuator. The experimental results show that the adaptive positive position feedback controller proposed in this paper can suppress vibrations even when the target structure undergoes structural change thus validating the approach.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• 대한의용생체공학회:의공학회지
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• 제15권3호
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• pp.281-288
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• 1994

In this paper, a new decomposition method of the interference EMG signal using MAMDF filtering and digital signal processor. The efficient software and hardware signal processing techniques are employed. The MAMDF filter is employed in order to estimate the presence and likely location of the respective templates which may include in the observed mixture, and high-resolution waveform alignment is employed in order to provide the optimal combination set and time delays of the selected templates. The TMS320C25 digital signal processor chip is employed in order to execute the intensive calculation part of the software. The method is verified through a simulation with real templates which are obtain ed from needle EMG. As a result, the proposed method provides an overall speed improvement of 32-40 times.

• 대한의용생체공학회:의공학회지
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• 제6권2호
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• pp.15-22
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• 제어로봇시스템학회지
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• 제4권2호
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• pp.15-17
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• 1998

DSP(Digital Signal Processor)는 신호처리의 응용에 있어서 실시간 처리가 요구되는 경우 탁월한 성능을 나타낸다. 멀티미디어 서비스를 위해서는 전송되어 들어오는 데이터를 빠른 시간에 처리를 하여 원하는 서비스를 제공해야 한다. 따라서 사용자 측에서는 전송된 데이터의 실시간 처리를 위한 특별한 장치가 요구된다. 본 논문에서는 이러한 용도를 위해 DSP를 이용하여 MSP(Multimedia Signal Processor)를 설계한다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1989년도 한국자동제어학술회의논문집; Seoul, Korea; 27-28 Oct. 1989
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• pp.962-966
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• 1989

A Digital Signal Processor (abbreviated to DSP) is used not only for digital signal processing but also for kinematic controls[l]. Then applications to these fields are expected to be developed. We propose a function calculation method on DSP which occupies no table memory. By using these functions, more fast or more accurate control will be achieved without using function table.