• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1222-1230
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• 2022

As the number of signal sources with low detectability by using various modulation techniques increases, research to classify signal modulation methods is steadily progressing. Recently, a Convolutional Neural Network (CNN) deep learning technique using FFT as a preprocessing process has been proposed to improve the performance of received signal classification in signal interference or noise environments. However, due to the characteristics of the FFT in which the window is fixed, it is not possible to accurately classify the change over time of the detection signal. Therefore, in this paper, we propose a CNN model that has high resolution in the time domain and frequency domain and uses wavelet transform as a preprocessing process that can express various types of signals simultaneously in time and frequency domains. It has been demonstrated that the proposed wavelet transform method through simulation shows superior performance regardless of the SNR change in terms of accuracy and learning speed compared to the FFT transform method, and shows a greater difference, especially when the SNR is low.

• Proceedings of the Korean Nuclear Society Conference
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• 2005.10a
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• pp.1071-1072
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• 2005

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.276-281
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• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.12
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• pp.31-39
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• 1993

In the playback signal processing of a digital magnetic recording system, the major signal processing processes consist of pulse equalization. pulse detection, clock recovery, and data recovery. Equalizer which compensates interference occurrde between pulses recorded in high density on a magnetic media is realized by pulse slimming method, and pulse detection by a integrating detector. Clock recovery from the detector output was accomplished by using PLL. and data recovery to reduce noise effects was carried out by utilizing the three sampling clocks recovered in clock recovery process. In this paper these processes are implemented in hardware and its performance is evaluated by experimenting with a commercial DAT. It was found that the playback signal processor proposed is suitable to the practical high density magnetic recording system.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.99-105
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• 2009

This paper suggests novel signal processing methods for optimal beamforming of smart antenna system in CDMA2000 mobile communication environments. This method utilize characteristics of the reverse pilot channel of CDMA2000 mobile communication systems, and applies them to improve the performance of an adaptive algorithm, which is used to a smart antenna system for beamforming. To perform the best beamforming, it is important to get an exact beamforming algorithm. This paper proposed an algorithm based on Laglange multiplier which has such an adaptive process, and also proposed the method to demodulate the received signal through array antenna using pilot channel in CDMA2000 environment. This paper analysed the enhanced performance of proposed algorithm in various signal environment through signal modeling of physical layer in CDMA2000 reverse link.

• Journal of the Korean Society of Safety
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• v.6 no.2
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• pp.21-30
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• 1991

In this paper, we study effect of waveness at the optical surface roughness measurement. In generally, waveness components cause errors in calculation of the roughness value of metal surface. We study about surface roughness signals In the frequency domain for separate two signal component of real roughness and waveness by digital signal processing methods. Thereafter, determine low and high Component of frequency spectrum. By this separating frequency value we design liner low and high pass filter which cutoff frequency is 1 Hz. After this process, converted each filtered spectrum by inverse discrete fourier transformation to time domain waveness and real roughness signals We calculate surface roughness value from filtered roughness signals. For evaluate this method, we use five specimens roughness signal which obtained from optical surface roughness measuring system in 3mm/s moving speed with 0.1 mm laser beam spot size As a result, we obtain more linerized roughness value than that of unfiltered roughness signals.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.5
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• pp.817-826
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• 2001

In this paper, we implemented QPSK(Quadrature Phase-Shift Keying) modem which is widely used for communication systems, using a general Digital Signal Processor(DSP), TM320C31. Up to now, almost all of communication systems consist of hardware. However, the implemented system herein is composed of software and hardware part. Software part includes the modulation process, before passing D/A(Digital-to-Analog Converter) and the demodulation process, after passing A/D(Analog-to-Digital Converter) in IF(Intermediate Frequency) node. Hardware part is related to input, output and process of signal. To demonstrate the successful implementation of modem, the output results obtained from DSP processor are compared with the simulated result on the personal computer.