• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.35 no.2
• /
• pp.47-54
• /
• 1986

Hardware implementation of a 32-channel MFC digital receiver has not been easy and simple, because it requires real time processing of PCM data. In this paper, we introduce a method of designing an MFC digital receiver compactly by the channel distribution method. We have implemented the MFC digital receiver to process many cnannels by distributing channels of the TDM input data directly to the commercial digital signal processor chips(NEC uPD7720), and by carrying out the modified Goertzel Algorithm. The design of low cost, reliable, high speed, and compact MFC receiver will be shown.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.10a
• /
• pp.973-976
• /
• 2009

Digital signal processing technique use to variety fields including communication. For these signal processing, FIR digital filter is representative. And for FIR digital filter designing, the window function is used to reduce the Gibbs phenomenon which occurs in the coefficient cutting process of the ideal filter. Therefore, in this paper to improve performance of digital filter, a high-order window function was applied. In this simulation, we compared a peak side-lobe and a transient characteristics with the existing window function.

• ETRI Journal
• /
• v.29 no.6
• /
• pp.835-837
• /
• 2007

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.5
• /
• pp.1349-1359
• /
• 1998

In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.3 no.2
• /
• pp.65-70
• /
• 2008

Digital signal processing (DSP) is the process of taking a signal and performing an algorithm on it to analyze, modify, or better identify that signal.[1] To take advantage of DSP advances, one must have at least a basic understanding of DSP theory along with an understanding of the hardware architecture designed to support these new advances. There are several programming techniques that maximize the efficiency of the DSP hardware, as well as a few fundamental concepts used to implement DSP software. This article introduced some of these underlying functions that are the building blocks of complex signal processing functions, and It will touch on the fundamental concepts of DSP theory and algorithms and also provide an overview of the implementation and optimization of DSP software, and discuss the development of DSP.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.868-871
• /
• 2002

Nowadays, zerotrees based digital watermarking techniques are considered to be an efficient watermarking technique used for multimedia data in a compressed form. This paper presents a technique for watermarking an image, by employing zerotrees derived from the wavelet packet coefficients of the transformed image to carry the watermark signal. By setting a proper threshold in zerotrees determining process, the watermark signal can be recovered without the need of original image. With our proposed technique, more amount of watermark signal can be embedded within the image, compared to ordinary wavelet transform based techniques. The experimental results show the improved performance in both qualities of the resultant watermarked image and robustness of the embedded watermark signal against common signal processing such as brightness/contrast enhancement, high-pass filtering, Gaussian noise adding and JPEG compression scheme

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.49 no.11
• /
• pp.933-940
• /
• 2021

The space-borne SAR(Synthetic Aperture Radar) system radiates the microwave signal and receives the backscattered signal. The received signal is converted to digital at the Digital Receiver, which is implemented at the end of the SAR sensor receiving chain. The converted signal is formated after signal processing such as filtering and data compression. Two quantization are conducted in the Digital Receiver. One quantization is an analog to digital conversion at ADC(Analog-Digital Converter). Another quantization is the BAQ(Block Adaptive Quantization) for data compression. The quantization process is a conversion from a continuous or higher bit precision to a discrete or lower bit precision. As a result, a quantization noise is inevitably occurred. In this paper, the impact of two quantization processes are analyzed in a view of SNR degradation.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.3
• /
• pp.96-105
• /
• 1992

The use of fixed-point digital signal processors, such as the TMS 320C25, requires scaling of data at each arithmetic step to prevent overflows while keeping the accuracy. A software which automatizes this process is developed for TMS 320C25. The programmers use a model of a hypothetical floating-point digital signal processor and a floating-point format for data representation. However, the program and data are automatically translated to a fixed-point version by this software. Thus, the execution speed is not sacrificed. A fixed-point variable has a unique binary-point location, which is dependent on the range of the variable. The range is estimated from the floating-point simulation. The number of shifts needed for arithmetic or data transfer step is determined by the binary-points of the variables associated with the operation. A fixed-point code generator is also developed by using the proposed automatic scaling software. This code generator produces floating-point assembly programs from the specifiations of FIR, IIR, and adaptive transversal filters, then floating-point programs are transformed to fixed-point versions by the automatic scaling software.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.5
• /
• pp.9-16
• /
• 1997

This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.563-566
• /
• 2003

We have designed the power control unit which belongs to the power cabinet and controls the power supplied to Control Rod Drive Mechanism(CRDM) as a digital system based on Digital Signal Processor(DSP). The power control unit dualized as the form of Master/Slave has had its increased reality. The Central Process Unit(CPU) board of a power control unit possesses two Digital Signal Processors(DSPs) of the control DSP for performing the tasks of power control and system monitoring and the communication of the Control DSP and the Communication DSP. To accomplish the functions requested in the power control unit effectively, we have installed Field Programmable Gate Arrays(FPGAS) on the CPU board and have FPGAs perform the memory mapping, the generation of each chip selection signal, the giving and receiving of the signals between the power controllers dualized, the fault detection and the generation of the firing signals.