• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of Broadcast Engineering
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• v.24 no.3
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• pp.485-494
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• 2019

A software-driven real-time frequency de-modulator is implemented with the aid of universal-serial-bus (USB) type software defined radio dongle. An analog stereo frequency modulation (FM) broadcast signal is down-converted to the basedband analog signal then converted to digital bit streams in the USB dongle. Computer software such as Matlab, Python, and GNU Radio manipulates the incoming bit streams with the technique of digital signal processing. Low pass filtering, band pass filtering, decimation, frequency discriminator, double sideband amplitude demodulation, phase locked loop, and deemphasis function blocks are implemented using such computer languages. Especially, GNU Radion is employed to realize the real-time demodulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.1043-1049
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• 2005

In OFDM system suitable for high capacity high speed broadband transmission, ICI caused by phase noise degrades system performance seriously by destroying the orthogonality among subcarriers. In this paper, a new STFBC method combining ICI self cancellation scheme and antenna, time, frequency diversity is studied to reduce ICI effectively. CPE and ICI are analyzed by the phase noise linear approximation method in the proposed STFBC OFDM system. CIR, PICR and BER are discussed to compare the system performance degraded by phase noise of PLL. As results, STFBC method significantly reduces ICI. Furthermore, the SCI that usually happens in the traditional STBC, SFBC diversity coding method can be easily avoided.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.805-817
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• 1999

In this paper, the needs for introduction and adoption of MㆍHF DSC/NBDP system and for developments of its circuits and call sequences for use in the maritime mobile services for small-ships, leisure-ships and fishing ships are analyzed, discussed. Also design and implement for MㆍHF(1.6-4MHz) DSC/NBDP system is discussed. Most of casualties have been arisen from small-ships and fishing ships during last 5 years. So, the SAR schematic plans should been prepared to prevent casualties and facilitate the activities of SAR for those ships. DSC/NBDP for MㆍHF system is able to fulfill the roles of efficient SAR communication functions, and to advance the SAR system to small ships and fishing ships. This study is focused on the techniques of processing the DSC call sequences and the ARQ sequences of NBDP system. Especially ARQ sequences are expanded into processing of Korean letters, designed the call sequences and code conversion algorithm for Korean-code. It will be evaluated the availability of Korean-NBDP system. In designing the Transmitting circuits and Receiving circuits, for the carrier generation, DDS(Direct Digital Synthesizer) is used in stead of the Phase Locked Loop and frequency conversion by the mixer, BPF. And PSK modulation signals are directly generated by the controls of DDS, which show the characteristics of Spurious Free Dynamic Range are below -62dBc. Also, the monolithic U subsystem IC which provides various functional components, AD608 is used for designing the receiving circuitsㆍAnd the algorithm of Phasing methode for FSK demodulation are devised to process IF frequency 455kHz in the IF circuits.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.564-566
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• 2003

전력 계통에서 안정한 전력을 공급하는 것은 매우 중요하다. 전력 계통의 오류는 전압 및 주파수를 감시함으로써 검출 가능하다. 본 논문에서는 디지털 위상 고정 루프를 이용한 전력 계통의 주파수 측정 장치를 제안하고 이를 구현한 결과를 제시하고자 한다. 제안한 주파수 측정 장치는 위상 고정 루프의 기본요소로 구성된다. 위상분별기는 배타적 논리연산을 통해 위상오차를 검출하고 위상의 앞섬 및 뒤짐의 검출이 가능하도록 설계하였으며, 전력 계통의 주파수 동특성을 고려해서 3차의 루프 필터를 설계하였다. DCO는 출력 주파수의 분해능을 고려하여 입력 신호를 정확하게 추정할 수 있도록 설계하였다. 제안한 주파수 측정 장치의 성능을 검증하기 위하여 모의실험을 통해 주파수 변동량의 측정 범위 및 정확도를 검토하였으며, FPGA와 CPU를 포함하는 하드웨어를 구현하였다. FPGA에는 Verilog HDL로 디지털 위상 고정 루프의 위상분별기와 DCO를 구현하였으며 루프필터는 소프트웨어로 구현하였다. 제안한 디지털 위상 고정 루프의 성능 검증을 위해 정밀한 함수 발생기의 출력을 인가한 후 출력 주파수를 측정한 결과 및 전력 계통에 대한 실험 결과를 제시하였다.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1684-1686
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• 2005

As photovoltaic(PV) power generation systems become more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive power of load and PV system are closely matched, islanding detection by passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop(DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment in IEEE Std 929-2000 islanding test.